eASIC Corporation

ASIC-in-a-Box Design Kits
for Low-NRE 90nm NEW ASICs

eZ-IP Core Datasheets

eTools 8.1 for
eASIC Nextreme-2 NEW ASICs

Low-NRE
90nm NEW ASICs
Low-NRE
45nm NEW ASICs
Reducing FPGA
Cost & Power

eASIC 90nm NEW ASICs

Up to 5M Gates (350K Logic Cells) and up to 5.6Mb of bRAM.
Ideal for High Volume Applications

eASIC 45nm NEW ASICs

Up to 20M Gates (1.9M Logic Cells) and up to 30Mb of bRAM.
Ideal for High Density Applications

Reducing FPGA Cost

FPGA designers looking to reduce device cost or cost per channel frequently use eASIC devices as a lower cost and risk path versus standard cell ASIC.

Reducing FPGA Power Consumption

FPGA designers looking to reduce device power consumption or power per channel frequently use eASIC devices as a lower risk path to standard cell ASIC. eASIC devices enable up to 80% reduction in power consumption.

What's New

Jun 15, 2010 eASIC Appoints Richard Heye as Chief Operating Officer
May 13, 2010 eASIC Nextreme Used for Hardware Validation of Microsoft RemoteFX Technology

Testimonials

Fujitsu Advanced Technologies Ltd is pleased to see that eASIC is delivering a 45nm product. This New ASIC is able to deliver the right combination of performance, power and price combined with low up-front cost. We find the power reduction especially important as we look to add more functionality to our world-class ICT infrastructure products.

Low Cost FPGA, Low Power FPGA, Low NRE ASIC, High Speed Transceivers, H.256 Codec HD High Definition Solution, 90nm Nextreme NEW ASICs, 45nm Nextreme-2 NEW ASICs, eDiVeo, eDV9200