San Jose, California, October 8, 2001 — eASIC® Corporation today announced that it will use Numerical Technologies’ (NASDAQ: NMTC) patented phase-shifting technology to boost the performance of its eASICore® configurable logic fabric. Offering speed advantages over conventional standard cell technology, this innovative integrated circuit (IC) solution will also carry significant cost and time-to-market benefits. The two companies will work together to release a breakthrough configurable logic fabric enhanced by phase-shifting transistor gates.
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The 0.15 micron eASICore® test chip indicates high density and performance and features unique via-configurable I/Os

San Jose, California, August 20, 2001 — eASIC Corporation today announced that it has completed the implementation of its eASICore, a configurable logic core, using UMC’s 0.15µm,
7 metal-layer process. The eASICore test chip comprises 24 embedded cores (eCores), featuring about 600K configurable logic gates, and via-configurable I/O pads called eI/Os. The results of the eASICore testing indicate high performance and high-density, in accordance with the engineering characterization.
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The released 0.15 micron eASICore® features 600K configurable logic gates and offers via configurable IOs – eIO™

Design Automation Conference, Las Vegas, Nevada, June 18, 2001 — eASIC Corporation today announced that it has completed the design of its first 0.15 micron embedded configurable logic for fabrication at UMC. The tapeout includes an eASICore array, comprised of 24 eCores, featuring about 600K configurable logic gates, and via configurable IO pads called eIO. This eASICore, which could compose a mini-platform, is a high performance and high-density configurable logic core, aimed at accelerating the development cycle and supporting low-cost derivatives for various platform-based and System-on-Chip (SoC) designs. The eASICore is ideal for communication applications.
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eASICore® test chips offer high performance and high density

San Jose, California, May 8, 2001 — eASIC® Corporation, the technology innovator of configurable logic IP cores, today announced its eASICore® has been successfully proven in silicon, in the form of test chips, on UMC’s 0.18 micron, 6 metal-layer process. The initial manufacturing results show the eASICore® delivers both high performance and high density. Fabless companies as well as Integrated Device Manufacturers, that use UMC’s foundry services, can now have greater confidence when integrating the configurable embedded logic core, as it is proven in silicon.
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eASICore® test results in silicon indicate high performance and high density

San Jose, California, April 23, 2001 — eASIC® Corporation, the technology innovator of configurable logic IP cores, today announced that the company has successfully implemented its eASICore® in TSMC’s silicon at 0.18 micron, 6 metal-layer process. Clear indication of high performance and density of the eASICore® was obtainable following the completion of the engineering characterization. eASIC® provided the design data to TSMC for test chip fabrication used for qualifying the manufacturing process and eventually lowering the risk for the customer. This will enable Fabless companies as well as Integrated Device Manufacturers who use TSMC foundry services, to enjoy the eASICore® advantages of high performance, low development cost and design flexibility.
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IP/SoC Conference, Santa Clara, Calif., March 19, 2001 — eASIC® Corporation today announced that the company has implemented SynTest ATPG (Automatic Test Pattern Generator) tools for its eASICore™, a high-performance and high-density single-mask configurable core. These tools will allow eASIC users to improve testability and fault coverage, resulting in reduced defect levels and tester time. eASIC customers can use the SynTest DFT tools, Turbo-Scan-ATPG™ and TurboBIST-Memory™, to improve their design’s testability.
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