San Jose, California, April 30, 2002 — eASIC Corporation, a provider of innovative configurable logic cores for System-on-Chip, today announced the award of six patents for very high-density configurable logic technology. These patents cover the concept of programmable logic cell array with mask-customized interconnection, as well as the segmented multi-layer routing fabric customized with a single mask, and additionally some unique elements of the eASIC technology.
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The platform features 1.2 million configurable logic gates and includes via-configurable SRAMs and I/O cells

DesignCon 2002 Conference, Santa Clara, California, January 28, 2002 — eASIC Corporation today announced that it has completed tapeout of its 0.13 micron platform with embedded configurable logic and support modules. The 25mm2 platform design includes an array of 24 eASICore® blocks providing 1.2 million gates of configurable logic, 1Mbit of configurable SRAM, via-configurable I/O pads (eI/Os) and system controller to support arrays of eASICore modules. The eASICore product is licensable silicon IP aimed at providing SoC and ASIC designers with a cost-effective and fast-turn solution to cope with today’s deep submicron design challenges.
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eASICores Combine with Monterey’s System-Driven Physical Design Tools to Raise the Level of Physical Abstraction

SUNNYVALE, California – January 12, 2002 — Monterey Design Systems and eASIC Corporation today announced a strategic agreement to provide the industry’s first core-centric hierarchical design solution. The combination of eASIC’s eASICore® configurable cores and Monterey’s System-Driven Physical Design™ solution raises the level of physical design abstraction from gates to functional cores, providing dramatic improvements in designer productivity and turnaround time. Engineers at Monterey and eASIC have been working together over the past year to develop a core-based design environment that yields significant productivity gains for large ASIC and SoC designs.
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