San Jose, California, December 15, 2004 — eASIC® Corporation, a provider of Configurable Logic and Structured ASIC products, today announced that the company was granted an additional patent for its breakthrough technology. The patent entitled “Customizable and programmable cell array” (6,819,136), issued on November 16, 2004 by the United States Patent and Trademark Office, is a continuation of a previous patent (6,756,811) granted to eASIC in the area of chip customization. This patent protects the company’s unique configurable logic technology, which utilizes electrical programmable cells connected with lithography-defined custom interconnections. The patent also protects the use of a coarse-grain array fabric, where each cell comprises of flip-flops with some fine grain functions such as inverters or multiplexers used as logic gates.
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(The 100 finalists were chosen from 1,200 entries)

San Jose, California, December 7, 2004 — eASIC® Corporation, a provider of breakthrough Configurable Logic and Structured ASIC products, today announced that the company was awarded “Top 100 Most Innovative Companies” by Red Herring Inc., a media company whose mission is to cover innovation, technology, financing and entrepreneurial activity. The top 100 innovators were selected after a long and rigorous process of evaluating more than 1,200 entries. The Red Herring editorial team has chosen the finalists and the winners will be announced at Red Herring’s Fall Conference in Monterey, California on Dec. 6-8. The results will also be published in Red Herring’s Dec. 13 issue.
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(The NRE-free Structured eASIC First Family Member Meets the Target Characteristics)

Electronica, Munich, Germany, November 9, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced successful testing and characterization of the first Structured eASIC family member – FA600. The test chips, fabricated by a European IDM partner at 0.13 micron process, were used to test functionality and characterize timing and power for the Structured eASIC device. The FA600 is the smallest member of the company’s Structured eASIC product family. Structured eASIC products feature an innovative combination of FPGA-like flexibility and ASIC-like performance in a unique offering of NRE-free ASIC. The complete product family is scheduled for production release in Q1 2005.
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(In a study held by EE Times and eeProductCenter, Structured eASIC was ranked #1 on both “technical significance” and “usability”)

San Jose, California, October 7, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that its Structured eASIC was ranked the #1 Ultimate Product in the Logic & Programmable Logic category of a study held by EE Times and eeProductCenter, surveying over 1,300 engineers, in order to allow sharing their experience with peers. The results of the survey were published by EE Times quarterly supplement called Ultimate Products. eASIC was ranked #1 in both criteria of “technical significance” and “usability”.
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(30 Companies will Present Innovative Technologies to Exclusive Audience)

San Jose, California, September 22, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that the company was chosen to present at the Emerging Technologies Conference Showcase, organized by Technology Review, MIT’s Magazine of Innovation, on MIT’s campus, on September 29-30, 2004. A total of thirty companies were selected through a juried process led by Technology Review’s staff. eASIC will showcase its Structured ASIC technology, a novel electronic design architecture protected by 10 issued patents. This technology was developed to cope with major semiconductor design issues and allow high-performance and affordable product developments in today’s nanotechnology era.
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(The patent was granted for innovative single-via customizable multi-layer routing fabric)

San Jose, California, July 7, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that it has received its tenth patent entitled “Customizable and programmable cell array” (6,756,811), issued on June 29, 2004 by the United States Patent and Trademark Office. This patent protects eASIC’s routing fabric that uses a single via for customization and applies to any metal routing fabric that comprises at least three metal layers. With this addition, eASIC’s patent portfolio broadly covers the company’s Structured ASIC fabric that features FPGA-like SRAM-LUT logic programmability combined with segmented standard metal routing, customized by a single via layer. This patented technology allows eASIC to offer a fast-turn Structured ASIC with no NRE (Non Recurring Engineering) cost, effectively using the maskless customization technique of Direct-Write eBeam.
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(Industry veteran will help eASIC grow in the Structured ASIC space)

San Jose, California, June 17, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that Saiyed Atiq Raza, Founder, Chairman and Chief Executive Officer of Raza Microelectronics, Inc. has joined the company’s board of directors. Bringing unparalleled experience in the semiconductor industry, Raza will help establish eASIC as a leading Structured ASIC vendor.
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The Alliance Promotes Fast-Turn Structured ASIC Solution Integrating High-Performance Silicon, Powerful Design Tools Suite and Low-Risk Manufacturing

Santa Clara, California, June 7, 2004 — Flextronics Semiconductor, a business unit of Flextronics, the world’s leading Electronics Manufacturing Services (EMS) provider, has partnered with Magma® Design Automation Inc. (NASDAQ: LAVA) and eASIC® Corporation to provide an optimal structured ASIC solution.
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eASIC chose Golden Gate’s “Power Saving” EDA flow to provide customers with a comprehensive and efficient Structured ASIC solution

Santa Clara, California, June 5, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, and Golden Gate Technology, a developer of power driven physical design tools, today announced the adoption of two products from Golden Gate’s GoPower suite. The IC-Plan™ and PowerPlacer™ tools will be used for eASIC’s Structured eASIC array. With this cooperation, the partners will incorporate Golden Gate’s clock aware physical design into eASIC’s tools set for Structured ASIC, responding to the market requirements of less power consumption, reduced wire length and guaranteed routability. As part of the agreement, two of Golden Gate’s products, the advanced power managing floorplanner (IC Plan) and the advanced power reducing placer (PowerPlacer), will be integrated into eAISC’s tools kit for designer’s use.
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Caufield & Byers (Vinod Khosla, KPCB Partner is Joining eASIC Board of Directors)

San Jose, California, May 28, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced that it has secured $5million in equity financing from Kleiner Perkins Caufield & Byers, in a third round of funding. The previous funding rounds involved angel investors and semiconductor industry veterans. Vinod Khosla, who was named the Silicon Valley’s most successful venture capitalist, is joining eASIC Board of Directors.
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(The Structured eASIC test application was released to a European IDM partner for fabrication in 0.13 micron process technology)

San Jose, California, May 28, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced taping out of its first Structured ASIC array to be fabricated by a European IDM partner at 0.13 micron process technology. The taped-out array called FA1, is the smallest member of the company’s Structured eASIC product family. The initial parts will be used to characterize timing and power for the Structured ASIC fabric and cell libraries. The complete product family is scheduled to be released for production in early Q1 2005. This product is being co-developed with Flextronics Semiconductor who will also be offering Structured ASIC products and services.
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Stepping up from a Structured ASIC IP provider to a fabless semiconductor

San Jose, California, April 27, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced stepping up to the next phase in its business strategy of fabless semiconductor model. With this move, the company will offer Structured ASIC chips, while continuing to provide Structured ASIC technology as licensable IP core for embedding in System-on-Chip. This strategy allows eASIC to play both in the Standard Cell arena as well as in the emerging Structured ASIC market. eASIC’s innovative Structured ASIC technology provides ASIC designers with the unique advantages of free NRE (Non Recurring Engineering) and FPGA-like design re-configurability, in addition to other Structured ASIC benefits such as low-cost and fast turnaround time.
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San Jose, California, January 27, 2004 — eASIC Corporation, a provider of configurable Structured ASIC technology, today introduced a maskless customization approach aimed at eliminating NRE (non recurring engineering) cost for ASIC. The NRE and mask-set cost are removed since eASIC employs direct-write e-Beam approach rather than conventional mask lithography for IC customization. Due to the company’s innovative Via-customization technique, eASIC’s fabric yields about 10 times higher throughput from Direct-write e-Beam machines, compared to metal customization. This is made possible as Vias occupy about 1% area of the customization layer, while metal occupies at least 30%, thus reducing the time e-Beam machine needs to spend writing the customization. Moreover, only a single Via-layer is required for Structured eASIC customization, which further shortens the turnaround time and eventually cuts the cost.
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