Monday, 16 November, 2009
New eTools 8.0 Software Simplifies 45nm ASIC Design
Santa Clara, CA – November 16, 2009 – eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of its eTools 8.0 software suite for implementing 45nm eASIC Nextreme-2 designs. The eTools 8.0 tool suite delivers a robust ASIC grade design flow with the simplicity, ease of design, and a cost point that is normally associated with FPGA design tools. By focusing on ease-of-use, and low cost of entry, eASIC is now enabling designers to make a seamless transition to adopting eASIC Nextreme-2 devices as a lower cost and lower power alternative to FPGAs and a lower NRE alternative to traditional ASICs. Read the rest of this entry »
Wednesday, 28 October, 2009
eASIC Nextreme NEW ASICs Enhance Video System Performance by 50%
Santa Clara, CA – October 28, 2009 – eASIC Corporation, a provider of NEW ASIC devices, today announced that Mitsubishi Electric Corporation (Kyoto Works), a leading global manufacturer of display wall systems, has selected eASIC’s Nextreme NEW ASICs for its Seventy Series Display Wall Cube Systems. Mitsubishi Electric used eASIC’s Nextreme devices to replace existing gate-arrays and improve the video processing system performance by 50%. Read the rest of this entry »
Monday, 28 September, 2009
Design Kits Significantly Simplify ASIC Design
Santa Clara, CA- September 28, 2009 – eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of two ASIC-in-a-Box design kits that enable ASIC design to be widely accessible and thereby reverse the trend of declining ASIC design starts. Through simplifying the design flow, the design kits empower engineers who are unfamiliar with ASIC design to now complete designs at a fraction of the cost and time compared to traditional standard cell ASICs. Read the rest of this entry »
Sunday, 14 June, 2009
Companies Collaborate to Deliver Small Foot-print, low-cost, ColdFire Implementations
Santa Clara, CA – June 15, 2009 - eASIC Corporation, a provider of NEW ASICs devices, and IPextreme®, the company bringing famous IP (intellectual property) to system-on-chip designers worldwide, today announced the immediate availability of Freescale´s 32-bit V1 and V2 ColdFire processor cores for eASIC Nextreme NEW ASICs. The addition of the ColdFire processors and peripheral IP cores to eASIC´s eZ-IP core library, enables designers to implement small foot-print, ColdFire cores on fast turnaround eASIC Nextreme NEW ASICs and thus provide a low-cost entry point for creating customized ColdFire-based applications within consumer, medical, automotive, and industrial markets. Read the rest of this entry »
Wednesday, 10 June, 2009
eASIC Nextreme NEW ASIC Delivers High Performance, low cost Solution for at Speed Verification
Santa Clara, CA – June 10, 2009 – eASIC Corporation, a provider of low up-front development cost NEW ASICs, today announced that ARM [(LSE:ARM);(Nasdaq:ARMH)] has successfully validated it’s next-generation Cortex™-A9 MPCore™ multicore processor using eASIC’s Nextreme NEW ASICs. With eASIC Nextreme, ARM was able to perform at speed verification with significantly higher performance, and lower development cost compared to the high-end FPGA solution that was previously used. Read the rest of this entry »
Wednesday, 6 May, 2009
FFT and FIR Compiler Cores from eASIC and Steepest Ascent Simplify Migration of FPGA-based DSP designs
Santa Clara, CA – May 6, 2009 – eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of two new DSP IP cores, an FFT and FIR Filter Compiler, to accelerate it’s growing momentum into the high performance DSP market. The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint. The FIR Compiler core, available from eZ-IP Alliance partner Steepest Ascent can process data streams as high as 500 MSPS and with its optimized multiplier-less architecture is perfectly suited to eASIC Nextreme and eASIC Nextreme-2 architectures. The addition of mainstream DSP blocks to eASIC’s IP portfolio makes it easier for wireless and video/imaging system designers to rapidly migrate costly FPGA-based DSP designs to lower-cost, lower-power eASIC Nextreme Series NEW ASICs. Read the rest of this entry »
