eASIC nextreme




ColdFire V1 Processor

ColdFire V1 Processor



  • 32-bit processor core with 24-bit address bus
  • Unified instruction/data bus (AMBA 2 AHB)
  • Single-wire debug interface
  • Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
  • Independent, decoupled pipelines
  • 2-stage Instruction Fetch Pipeline (IFP)
  • 2-stage Operand Execution Pipeline (OEP)
  • FIFO Instruction Buffer is the decoupling mechanism
  • ColdFire Instruction Set Architecture Rev. C (ISA_C)
  • Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
  • Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
  • Static branch prediction mechanisms minimize change-of-flow execution time
  • Execute engines include ALU, barrel shifter, integer divider (DIV), and multiply accumulate unit (MAC)
  • Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)