eASIC nextreme




ColdFire V2 Processor

ColdFire V2 Processor



  • Variable-length RISC, clock-multiplied core
  • 166-MHz in typical 130-nm process
  • Independent, decoupled pipelines:
  • 2-stage instruction fetch pipeline (IFP)
  • 2-stage operand execution pipeline (OEP)
  • FIFO instruction buffer is the decoupling mechanism
  • 16 user-accessible, 32-bit general purpose registers (GPRs)
  • 32-bit data bus & 32-bit address bus supporting 4-GB linear addressing range
  • Sophisticated two-level branch acceleration mechanisms minimize change-of-flow execution time
  • Background Debug Mode (BDM), Real-Time Trace (RTT), and Real-Time Debug (RTD) support
  • Binary object code compatibility across the entire Freescale ColdFire Family
  • Optional Enhanced Multiply-Accumulate (EMAC) provides high-speed signal processing capabilities with four 40-bit accumulators and single-cycle instruction issue rate on 32-bit MAC operations
  • Vector base register to relocate the exception vector table
  • Integrated cache controller; cache is direct-mapped, configurable as instruction, data, or split instruction/data cache
  • Integrated SRAM controller
  • 100% synthesizable and technology-independent design
  • EDA tool-neutral packaging