eASIC nextreme




DDR2 SDRAM Controller Core & Phy

DDR2 SDRAM Controller Core & Phy



  • Maximizes bus efficiency via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
  • Minimal latency achieved via parameterized pipelining
  • Achieves high clock rates with minimal routing constraints
  • Supports full rate and half-rate clock operation
  • Full run-time configurable timing parameters and memory settings
  • Supports ODT and 2T timing
  • Full set of Add-On Cores available
  • Delivered fully integrated and verified with target DDR PHY
  • Minimal ASIC gate count
  • Source code available
  • Customization and Integration services available