DesignCon 2002 conference eASIC completes tapeout of 0.13 micron configurable platform
January 28, 2002
The platform features 1.2 million configurable logic gates and includes via-configurable SRAMs and I/O cells
DesignCon 2002 Conference, Santa Clara, California, January 28, 2002 — eASIC Corporation today announced that it has completed tapeout of its 0.13 micron platform with embedded configurable logic and support modules. The 25mm2 platform design includes an array of 24 eASICore® blocks providing 1.2 million gates of configurable logic, 1Mbit of configurable SRAM, via-configurable I/O pads (eI/Os) and system controller to support arrays of eASICore modules. The eASICore product is licensable silicon IP aimed at providing SoC and ASIC designers with a cost-effective and fast-turn solution to cope with today’s deep submicron design challenges.
“We view this release as a major milestone. As tooling cost at 0.13 micron approaches $1 million, high-density configurability is becoming mission-critical,” said Zvi Or-Bach, eASIC President and CEO. “Our 0.13 micron release comprises a full set of modules for platform-based design. Our eASICore and other IP components are designed to facilitate and accelerate SoC development for communications, networking and emerging market applications. This family of products enables the development of high-performance reconfigurable SoC.”
The patented eASICore technology allows for configurable logic blocks to be embedded into user designs in a fast, easy to implement, and cost-effective manner. This breakthrough technology combines SRAM-based logic cells with mask-customizable metal interconnection.
eASICore is a hard, configurable IP core that occupies 0.43 mm2 (in 0.13 micron technology) and implements about 50K logic gates in a single block. Arrays of eASICore blocks can be embedded in users’ SoC designs to support large amounts of rapidly configured logic. Users can implement designs on the eASICore using standard ASIC synthesis and Place & Route tools. The 0.13 micron configurable logic fabric uses the first 4 metal layers, leaving the top metal layers for interconnect. The customization of the eASICore logic is performed by bit-stream loading of the SRAM-based logic.
Two connectivity options are available:
- As few as 2 metal layers can be used for eASICore cell routing, reserving additional layers for over-the-cell routing.
- Alternatively, up to 4 metal layers can be used for eASICore cell routing, using either custom metal, or the patented eASIC routing structure that is customized using a single-via mask layer.
eASICore’s technology uses the Look-Up-Table approach to logic implementation proven in FPGA technology, while avoiding the deficiencies of SRAM-programmable interconnect. This is made possible by eASIC’s innovative single-mask configured, metal-to-metal interconnection. The cost/performance of eASICore is much better than FPGA, since the eASICore metal interconnect is dramatically smaller and faster than the SRAM-programmable interconnect used in FPGA technology. The eASICore delivers density and speed that are comparable to Standard Cell, with FPGA ease-of-design and time-to-market.
eASIC Corporation is pioneering a breakthrough approach of configurable logic cores for System-on-Chip and platform-based designs. Its configurable logic IP core, called eASICore, offers high performance and density with ease-of-design, rapid time-to-market and reduced development cost.
eASIC Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania.
eASIC’s technology is protected by US patents: US 6,194,912, US 6,236,229, US 6,245,634, US 6,331,733, US 6,331,789, US 6,331,790 and additional pending patents. See legal.
Contact: Jasbinder (Jazz) Bhoot
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