eASIC nextreme

eASIC and Tensilica Partnership Delivers Free Diamond Processors

eASIC and Tensilica Partnership Delivers Free Diamond Processors

November 26, 2007

Customized Tensilica-based Embedded Systems Now Available at Any Volume

SANTA CLARA, CA, – November, 26, 2007 – Tensilica®, Inc and eASIC Corporation today announced a partnership to remove the cost barriers for developing custom embedded System-on-a-Chip. (SoCs). Through this partnership eASIC now provides free access to Tensilica’s Diamond Standard microprocessor and DSP cores for its free mask charge, no-minimum order ASICs. This unique combination enables embedded system designers to develop Diamond processor-based SoCs for applications in any production volume. Designers will now be able to develop customized, highly differentiated ASIC solutions at a lower cost than FPGA-based embedded systems.

Tensilica’s processors range from a very small, low-power 32-bit controller up to the industry’s highest performance digital signal processing (DSP) core and a multifunction audio processor that has been designed into millions of cellular phones. The Diamond Standard family includes:

  • 106Micro – the industry’s smallest cachless, 32-bit RISC controller core
  • 108Mini – a small cachless 32-bit RISC controller with built-in DSP capabilities
  • 212GP – a flexible mid-range 32-bit RISC controller
  • 232L – a mid-range 32-bit CPU with Memory Management Unit (MMU) for Linux OS support
  • 570T – a high-end 32-bit CPU core
  • 545CK – a high performance DSP core
  • 330HiFi – a low-power, 24-bit audio DSP processor supported with popular audio and speech codecs

The Diamond Standard family covers the broadest range of performance of any embedded computing architecture and the processors are supported by an optimized set of Diamond Standard software tools and an extensive ecosystem of industry infrastructure partners. The Diamond Standard family is available to eASIC’s customers via the company’s eZ-IP Alliance program.

Free Tensilica processors on zero-mask charge structured ASICs is revolutionary breakthrough in reducing the upfront costs for customers looking to develop low-cost custom embedded processing systems at any volume, stated Jasbinder Bhoot, Sr. Director, Marketing at eASIC Corporation. This partnership is proof that a new era of system on a chip is upon us. No upfront cost and no minimum order quantity for an embedded processor core on a high-performance and volume-capable ASIC.

Several of our customers have been attracted to eASIC’s Nextreme Structured ASICs for fast prototyping or mass production, stated Chris Jones, Tensilica’s Director of Strategic Alliances. eASIC’s Structured ASIC technology offers customers a lower power, higher density solution than FPGAs at a much lower cost and faster time to market than cell-based ASICs.

About eASIC

eASIC is a fabless semiconductor company offering breakthrough zero mask-charge ASIC chips aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer ASICs with no mask-charges and no minimum order quantity.

Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Evergreen Partners and Advanced Equities Incorporated. For more information, please visit www.eASIC.com

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica’s patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.

Press Contacts:

For Tensilica:
Paula Jones
(408) 327-7343

Erika Powelson
(831) 424-1811

For eASIC:
Jasbinder Bhoot
(408) 855-3028

Editors’ Notes:

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names mentioned are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Afa Technologies, ALPS, Aquantia, Astute Networks, Atheros, AMD (ATI), Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Brocade, Cisco Systems, CMC Microsystems, Conexant Systems, EE Solutions, Epson, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, iBiquity Digital, Ikanos Communications, Intel, Juniper Networks, LG Electronics, Lucid Information Technology, Marvell, MedioPhy, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., Penstar, Plato Networks, PnpNetwork Technologies, SiBEAM, Silicon Optix, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, Valens Semiconductor, Validity Sensors, Victor Company of Japan (JVC), and XM Radio.