eASIC completes tapeout of its embedded configurable logic
June 18, 2001
The released 0.15 micron eASICore® features 600K configurable logic gates and offers via configurable IOs – eIO
Design Automation Conference, Las Vegas, Nevada, June 18, 2001 — eASIC Corporation today announced that it has completed the design of its first 0.15 micron embedded configurable logic for fabrication at UMC. The tapeout includes an eASICore array, comprised of 24 eCores, featuring about 600K configurable logic gates, and via configurable IO pads called eIO. This eASICore, which could compose a mini-platform, is a high performance and high-density configurable logic core, aimed at accelerating the development cycle and supporting low-cost derivatives for various platform-based and System-on-Chip (SoC) designs. The eASICore is ideal for communication applications.
Additionally, with the unique via configurable IO capability (eIO), all available IOs of comparable Standard Cell libraries are provided based on a single generic IO structure, configured through a single custom via layer. The eIO feature adds I/O flexibility to the platform design.
“We see an ever increasing need for configurability, speed and flexibility for deep sub-micron SoC designs,” said Zvi Or-Bach, eASIC President and CEO. “The embedded configurable logic core is an emerging technology that provides an answer to these market requirements. Since tooling cost approaches $1 million, it’s mission critical to use configurable logic cores to react quickly to market fluctuation, while saving cost and extending the design life cycle. With its high logic density and performance, the eASICore turns out to be the missing building block for SoC platform. Such a platform could use a single silicon base set for a range of high volume applications.”
eASIC’s configurable logic core (eASICore) is a hard, configurable IP, of about 25K useable logic gates. Users can map arbitrary logic onto the eASICore using standard ASIC synthesis tools, and perform placement and routing using standard ASIC P&R tools. The customization of the eASICore is performed by bit-stream loading of SRAM-based logic and custom mask for the interconnect. The 0.15 eASICore, implemented in UMC’s 7 metal-layer process, uses the lower 3 metal layers for the logic fabric, leaving 4 metal layers for interconnects. Two connectivity options are available:
- For a small array of eASICores, two metal layers could be used for the eASICore while reserving the top two for over-the-cell routing.
- For a large array of eASICores, all four metal layers could be used for the eASICore interconnections, utilizing a patent pending single-via mask-customization.
The eASICore includes a built-in low-skew, low-power, clock tree and built-in scan chain.
eIO – Via-Configurable IO Pads
The eIO – via-configurable IO pad – is an innovative technique developed to allow an additional level of flexibility for platform-based designs utilizing eASICore’s technology. Each pad can be configured as INPUT, OUTPUT, BI-DIRECTIONAL or SUPPLY.
Using only via-configuration, the pad characteristics can be changed as follows:
The INPUT section can be programmed for:
Type: regular CMOS/LVTTL or Schmitt
Inversion: non-inverting or inverting
The OUTPUT section can be programmed for:
Keeper: pullup, pulldown, or keeper
Drive: 2 to 24 mA in 9 steps
Slew: normal or slow
The SUPPLY section can be programmed for:
GND: Ground to core and input IO section
VDD: Power (1.5V) to input IO section
VDDE: Power (1.5V) to chip core
VCC: Power (3.3V) to output IO section
VSS: Ground to output IO section
eASICore’s architecture is built on a proprietary technology that allows embedding configurable logic blocks in a fast, easy to implement and cost-effective manner. The concept of this breakthrough technology is of an SRAM Look-Up-Table cell combined with mask-customizable interconnection. With this structure, eASICore delivers close to Standard Cell performance and density together with FPGA time-to-market and ease-of-design. Moreover, eASIC’s technology resolves the issues of huge silicon area and circuit delay resulting from programmable interconnect in existing FPGA technologies.
eASICore’s underlying technology takes advantage of the already proven Look-Up-Table approach for logic implementation, while avoiding the deficiencies of SRAM programmable interconnect. This is made possible due to eASICore’s interconnect, which is mask-configured, providing metal-to-metal interconnection. The benefit is in using a much smaller silicon area, and consequently reducing SoC production cost. Furthermore, the resulting delay of the eASICore interconnect is significantly (10 to 100 times) lower compared to SRAM programmable interconnect.
The 0.15 micron eASICore is scheduled to be tested in early Q3 2001 on UMC silicon and will be available for customers in the second half of 2001.
eASIC Corporation is pioneering a breakthrough approach of embedded configurable logic for System-on-Chip and platform-based designs. Its configurable logic IP core, called eASICore, offers high performance and density with ease-of-design, rapid time-to-market and reduced development cost.
eASIC Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania.
Contact: Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201