eASIC Delivers 45nm Zero Mask-charge New eASIC Family
August 4, 2008
eASIC Nextreme-2 New ASIC Family Aimed At Reversing Decline of Worldwide ASIC Design Starts
Santa Clara, CA – August 4, 2008 – Leveraging the rapid success of its award winning 90nm eASIC Nextreme ASIC Products, eASIC Corporation today announced its next generation eASIC Nextreme-2 Family – the semiconductor industry’s first 45nm, zero mask-charge New ASIC family.
The eASIC Nextreme-2 Family delivers on eASIC’s promise of affordable silicon customization, enabling the design of custom chips using state-of-the-art 45nm technology and the delivery of working devices in only six-weeks. eASIC is currently engaged with early access customers, and mainstream availability will commence in the fourth quarter of 2008.
“Fujitsu Advanced Technologies Ltd is pleased to see that eASIC is delivering a 45nm product,” said Akira Itoh, Director of the Fujitsu Circuit Technology Center of Fujitsu Advanced Technologies Ltd. “This New ASIC is able to deliver the right combination of performance, power and price combined with low up-front cost. We find the power reduction especially important as we look to add more functionality to our world-class ICT infrastructure products.”
The no-minimum order quantity eASIC Nextreme-2 ASIC Family paves the way for accelerating eASIC’s market expansion into the $85 billion global logic market, the worldwide semiconductor industry’s largest sector.
“Gartner has tracked ASIC design starts for years and the trend has been unmistakable, downward to the right,” says Bryan Lewis, Research VP at Gartner. “Leading edge ASIC design costs have risen to the point where many small- to- medium sized companies have no choice but to use FPGAs. New approaches are being developed that lower ASIC design costs and have the potential to bring the benefits of ASICs back to the masses.”
eASIC Nextreme-2 Family – World’s Only 45nm, Zero Mask-Charge ASIC
- Up to 80 percent lower power than FPGAs
- Up to 20M gates
- Up to 30 Mbits of true dual-port memory
- Up to 2.4 TeraMACs of DSP performance
- Up to 56, 6.5Gbps transceivers & 1.25Gbps LVDS
- Simple design tools and flow
- Six weeks to silicon devices
- No minimum order quantity
“Judging from the magnetic draw we are seeing from the market, we are confident that FPGA designers, ASIC designers and semiconductor companies will find eASIC Nextreme-2 to be an irresistible platform for their new designs,” said Ronnie Vasishta, President and CEO of eASIC Corporation. “The New ASIC era of high performance, low power and dramatic cost reduction with fast time-to-market is just beginning, and we are already driving a reversal in the trend of declining design starts.”
The eASIC Nextreme-2 Family is manufactured on Chartered Semiconductor’s 45nm low-power (LP) process and armed with the industry’s most efficient LUT-based architecture. The logic fabric provides up to 700MHz performance enabling signal processing engineers with an impressive 2.4 TeraMACs of DSP capability without the need for embedded multipliers.
The combination of triple oxide transistors, 45nm LP process and eASIC’s patented power-management architecture enables eASIC Nextreme-2 to lower power consumption by up to 80 percent when compared with state-of-the art FPGAs. Low-power consumption makes eASIC Nextreme-2 an ideal choice for applications that demand power efficiency to help reduce system cost and meet stringent power budgets. The eASIC Nextreme-2 Family also includes up to 56 MGIO’s (multi-Gigabit IOs) each capable of operating at 6.5Gbps providing 364Gbps bandwidth. The inclusion of the MGIO’s makes eASIC Nextreme-2 a compelling alternative to FPGAs and ASICs for high performance networking applications such as switches, routers, traffic management, metro transmission and mobile backhaul. eASIC Nextreme-2 delivers ASIC performance with rapid turnaround time and low upfront cost.
eASIC is a fabless semiconductor company offering breakthrough zero mask-charge, no minimum order quantity New ASIC devices dramatically reducing overall cost and production times for customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information, please visit www.eASIC.com.