The Fast Fourier Transform (FFT) is a fundamental building block used in DSP systems, with applications ranging from OFDM based Digital MODEMs, to Ultrasound, RADAR and CT Image reconstruction algorithms. Although its algorithm is quite easily understood, the variants of the implementation architectures and specifics are significant and are a large time sink for hardware engineers today.

The FFT v1.0 provides two different FFT architectures along with a system level fixed point C-model, and can be a drop-in replacement for FPGA Designs. To enable easy understanding of the core during simulation and design testing, RTL Verilog is provided.

Key Features of FFT/iFFT:

• Performance up to the 300 MHz max in eASIC Nextreme-II Devices
• Performance up to the 190 MHz max in eASIC Nextreme Devices
• Maximum Throughput of 90 MSPS in eASIC Nextreme-II and 54 MSPS in eASIC Nextreme
• Transform sizes from 8 to 16K points with the option to be run-time programmable
• Two architectural implementation options providing the most area efficient implementation for a given data rate
• A fixed point bit-accurate C-Model to enable system level analysis of eASIC FFT core
• Drop in replacement for FPGA FFT IP to simplify cost and power reduction transition to eASIC
• Bit width trade off (8-18 bits) enable a resource efficient implementation given the algorithmic constraints
• Run-time configurable forward or inverse operation and scaling schedule
• RTL Verilog Code keeps design transparent and open to the user

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