Steepest Ascent’s High-Speed FIR Filter Compiler generates digital filter implementations based on fully pipelined transpose form FIR architecture with a highly optimized multiplier block and summation chain. This structure allows the generated filters to be operated at very high clock rates and sampling rates with extremely low hardware cost. The filter compiler supports both multi-channel and multi-rate filter types making it ideal for applications such as digital upconversion and downconversion

Key Features

• Generates single-rate and multi-rate (interpolation / decimation) filters
• Single-channel or multi-channel operation, applicable to both single-rate and multi-rate operation
• Multi-rate filters are implemented using polyphase decomposition techniques
• Highly optimized multiplier block synthesis
• Automatic optimization of symmetric and halfband filter types
• Filter designs provided in VHDL
• Realizes user specified filters with very low hardware cost
• Fully pipelined implementation yields very high clock rates and sampling rates
• Full-precision word length at all arithmetic stages through to the output
• Supports signed or unsigned input samples and signed or unsigned coefficients with configurable word lengths

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