This DES Crypto-processor core is a fully compliant implementation of the DES encryption and decryption algorithm. This design is a simple, fully synchronous design core. It can be used in many applications including: electronic financial transactions, secure communications, secure video surveillance systems and encrypted data storage.

Key Features:

• NIST certified 56 bit DES implementation.
• Both encryption and decryption supported.
• Encryption and decryption performed in sixteen clock cycles.
• No dead cycles for Key loading or mode switching.
• High clock speed and low gate count achieved.
• Sustained bit rate is 4x clock speed.
• Suitable for data security applications.
• Fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.

Download Datasheet

You do not have permission to download this file. Please login or register