This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1. It computes a 160-bit message digest for messages of up to (2₆₄ – 1) bits. Applications for this core include: electronic funds transfer, authenticated electronic data transfer and encrypted data storage.

Key Features:

• Suitable for data authentication applications.
• Fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core

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