The I2C core implements a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus. The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (I2CSTA) reflects the status of I2C Bus Controller and the I2C bus.

Key Features:

• Master Transmitter Mode: data output through SDA while SCL outputs the serial clock.
• Master Receiver Mode: Serial data is received via SDA while SCL outputs the serial clock.
• Slave Receiver Mode – Serial data and the serial clock are received through
  SDA and SCL
• 7-bit addressing format
• Slave Transmitter Mode – Serial data is transmitted via SDA while the serial
  clock is input through SCL
• Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode.
• Bi-directional data transfer
• Own address and General Call address detection.

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