This core implements a PCI Express end point controller that is compliant with PCI ExpressBase specification 1.0a, including the transaction, Data Link, and Physical protocol layers. The scalable and flexible core has a modular architecture and a high-performance,low-latency design.

Key Features:

• Compliant with PCI Express Base Specification 1.0a
• Implements Transaction, Data Link, and Physical protocol layers in hardware
• Supports x1 and x4 link widths
• Offers a data rate of 2.5 Gbps per lane
• Supports up to eight Virtual Channels
• Supports lane reversal and polarity inversion
• PCI Configuration space type 0 header
• MSI capability support
• End-to-end cyclic redundancy code (ECRC) generation and checking support
• Advanced Error Reporting capability support
• Configurable TLP data payload size, from 128B to 4kB. Configurable Transmit Retry and Receive data buffers
• Modular architecture, synchronous design
• 64-bit internal datapath at 125MHz
• Support for asynchronous application and core clocks
• Easy system integration through generic interface or industry standard bus interfaces module with up to 8 DMA channels (e.g., Wishbone, AMBA)
• Conforms to standard PIPE interface for compatibility with any 16-bit PIPE-compliant PHY.

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