ASIC Architect’s PCI Express IP Cores are silicon-proven, highly configurable, scalable and ready to meet your custom design requirements.

The cores come in multiple application interface data path flavors with the choice of 8-bit or 16-bit PIPE PHY Interface. The cores have been architected to achieve very low latency, high throughput, and quick timing closure with a very small silicon footprint. The user interface provides practical and integration-friendly mechanisms for the integration of the cores to the user logic.

Key Features:

• Multiple listings in the PCI-SIG Integrator’s list
• Low Latency: Less than 11 clock cycles
• Lanes Supported: x16, x8, x4, x2, x1
• Optionally Legacy Mode Support
• Multifunction Support up to 8
• Multi VC Support up to 8
• High Performance with Low Latency, Maximum Throughput
• Multiple Pipelined Memory WR/RD Capability
• Low Silicon Footprint
• Highly Parameterized Core supporting both cut-through and store-and-forward schemes
• Supports operation with 8-bit and 16-bit PIPE interface
• Implements all optional configuration space and capability structures
• Configurable Retry buffering scheme for low footprint and latency
• Supports all power management states L0, L0s, L1, L2 & L3
• Supports PCI Express Advanced Error Reporting
• The products support the most advanced features in PCI Express – Power Management,
  QoS, Hot-Plug & Hot-Swap, Data Integrity, and Error Handling.

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