The WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IPCores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. This is accomplished by creating a common interface between IPcores. This improves the portability and reliability of the system, and results in faster time-to-market for the end-user.

Key Features:

• Simple, compact, logical IP core hardware interfaces that require very few logic gates.
• Supports structured design methodologies used by large project teams.
• Full set of popular data transfer bus protocols including:
  • READ/WRITE cycle
  • BLOCK transfer cycle
  • RMW cycle
• Modular data bus widths and operand sizes.
• Supports both BIG ENDIAN and LITTLE ENDIAN data ordering.
• Variable core interconnection methods support point-to-point, shared bus,
  crossbar switch, and switched fabric interconnections.
• Handshaking protocol allows each IP core to throttle its data transfer speed.
• Supports single clock data transfers.

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