Northwest Logic’s DDR SDRAM Controller Cores is part of a complete Memory Interface Solution including Add-On Cores and eASIC specific DDR PHY. This solution provides very high DDR SDRAM bus performance with minimal latency. This solution is modular enabling it to be easily configured for a target application with minimal logic usage. The core fully supports the eASIC Nextreme family of devices.

Key Features:

• Supports 400 Mbit/s operation in eASIC Nextreme device
• Supports full range of memory configurations (on-board chips, DIMMs, etc.)
• Provides high bus efficiency
• Minimum latency achieved via parameterized pipelining
• Minimal logic size
• Simple, easy-to-use interfaces
• Full suite of add-on cores available – AHB/AXI Interface, Multi-Port, RMW, ECC, Memory Test, etc.
• Integrated with eASIC specific DDR PHY
• At-speed FPGA prototyping supported
• Provided as source code with expert technical support
• Customization & Integration services available

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