ASIC Architect’s DDR and DDR2 Controller IP Cores are an integral part of the product portfolio aimed at providing a complete end-to-end solution in the High Speed Interface Controller domain. The DDR and DDR2 Controller Cores are architected, designed and verified by ASIC/SoC industry veterans. The add-on solution cores that come with the DDR Controller, accelerate the chip-level integration by connecting multiple clients to the DDR Controller.

Key Features:

• Supports up to 533MHz in DDR2 Mode
• Powerful Application Interface
• Supports both DDR and DDR2 JEDEC Standards
• Addressing capability upto 4GB DDR2 devices
• Programmable Features:
  • Memory timing parameters – Tras, Trdl, Tccd, Trfc, Tmrd, Trp, Tcrd
• Intelligent Bank Management
• Supports buffered and unbuffered DIMMs
• Supports On-die termination (ODT), and Off-Chip Driver impedance adjustment
• Configurable Features:
  • Address Mapping between application bus and row/column/bank addresses
  • Choice of 16/32/64-bit DDR bus-width
  • Size of Command Queue
• Supports additive CAS latency feature to maximize command bus utilization
• Supports Back-to-Back WR & RD with minimum time intervals
• High data rate up to 100% memory throughput
• Byte-wide optional ECC Support
• Auto initialization of DDR Memories
• Byte-Wide Data Mask Support
• Self-refresh and power down control
• Fully ATPG Testable – Multiple Clock Domains
• Supports industry standard memory vendors
• Low Latency
• Verified with leading memory and IO vendors
• Supports Multiple Application Clients
• Optionally connects to AMBA® 3 AXI™ bus

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