eASIC Corporation > IP Cores > Memory Controllers > OpenCores SPI Master Core

OpenCores SPI Master Core

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Synchronous serial interfaces are widely used to provide board-level interfaces between different devices such as microcontrollers, DACs and ADCs and. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations, namely, SPI and Microwire/Plus.

Key Features:
  • Full duplex synchronous serial data transfer
  • Variable length of transfer word up to 128 bits
  • MSB or LSB first data transfer
  • Technology independent Verilog
  • Fully synthesizable
  • Rx and Tx on both rising or falling edge of serial clock independently
  • 8 slave select lines
  • Fully static synchronous design with one clock domain
  • Technology independent Verilog
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