LEON4 Processor

The LEON4 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-chip (SOC) designs. LEON4 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores.

The LEON4 is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Aeroflex Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and eASIC device technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL, MAC and DIV instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU).

The LEON4 cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

The LEON4 pipeline uses 64-bit internal load/store data paths, with an AMBA AHB interface of either 64- or 128-bit. Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1.7 DMIPS/MHz, or 2.1 CoreMark/MHz.

LEON4 Key Features

The LEON4 processor has the following features:

• SPARC V8 instruction set with V8e extensions
• Advanced 7-stage pipeline, with branch prediction
• 64-bit single-clock load/store operation
• 64-bit 4-port register file
• Hardware multiply, divide and MAC units
• High-performance, fully pipelined IEEE-754 FPU
• Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Configurable caches L1: 1 – 4 ways, 1 – 256 kbytes/way. Random, LRR or LRU replacement
• Configurable L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte – 8 Mbyte
• SPARC Reference MMU (SRMMU) with configurable TLB
• AMBA-2.0 AHB bus interface, 64- or 128-bit wide
• Advanced on-chip debug support with instruction and data trace buffer, and performance counter
• Symmetric Multi-processor support (SMP)
• Power-down mode and clock gating
• Robust and fully synchronous single-edge clock design
• Up to 150 MHz in FPGA and 1500 MHz on 32 nm eASIC device technologies
• Extensively configurable
• Large range of software tools: compilers, kernels, simulators and debug monitors
• High performence: 1.7 DMIPS/MHz, 2.1 CoreMark/MHz, 0.35 SPECint2000/MHz

LEON4 Configuration

The LEON4 processor is fully parameterizable through the use of VHDL generics, and does not rely on any global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations.

LEON4 Software Development

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON4 (kernels will need a LEON BSP). To simplify software development, Aeroflex Gaisler is providing BCC, a free C/C++ cross-compiler system based on gcc and the Newlib embedded C-library. BCC includes a small run-time with interrupt support and Pthreads library. For multi-threaded and/or multi-processor applications, a LEON port of the eCos real-time kernel is available. A LEON port of RTEMS is available in form of the RCC cross-compiler, a system that supports RTEMS for LEON3 and LEON4. For industrial and high-rel applications, ports for Nucleus and VxWorks 6.7 are available, as well as ThreadX.

Linux support for LEON4 is provided through a special version of the SnapGear Embedded Linux distribution. SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. The LEON4 port of SnapGear supports the MMU, as well as the optional V8 mul/div instructions and floating-point unit (FPU). A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration. The latest version of SnapGear also includes multi-processor support (SMP) for multi-core LEON4 systems.

Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. Aeroflex Gaisler provides TSIM, a high-performance LEON4 simulator which seamlessly can be attached to gdb and emulate a LEON4 system at more than 30 MIPS. The GRMON monitor interfaces to the LEON4 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway. For multi-processor and/or advanced SOC designs, the GRSIM multi-core simulator is available for early software development.

LEON4 Evaluation

A ready made eASIC device with a dual-core LEON4 processor system is available with an evaluation board.

GR-LEON4-ITX LEON4 Development Board

The GR-LEON4-ITX evaluation board has been designed to support development and fast prototyping of systems based on the Aeroflex Gaisler multi-core LEON4 processor. The LEON4 processor is a synthesizable VHDL model of a 32-bit processor compliant to the SPARC V8 architecture.

This evaluation board, incorporating a dual-core LEON4 eASIC device with several serial and parallel interfaces, is capable of operating stand-alone, as a demonstration single board computer, or can be extended with standard PCI card functions. The incorporation of on-board volatile and non-volatile memories, together with PCI host slots, USB and Ethernet interfaces makes this board ideal for evaluating the dual-core LEON4 system-on-chip design and for software development.

Features

The LEON4 processor has the following features:

• Mini-ITX format mainboard with dual PCI slots
• LEON4 SOC eASIC device:
  • Dual LEON4 cores @ 200 MHz, IEEE-754 FPU, MMU, MUL/DIV units
  • 64-bit AHB bus
  • Large range of on-chip cores: USB-2.0, SVGA, SPI, Ethernet, PCI, PS/2, I2C, CAN
• On-board memory:
  • 256 Mbyte 32-bit DDR2-400 SDRAM
  • 8 Mbyte SPI Serial Flash PROM
• Interfaces:
  • Dual 32-bit 33 MHz PCI mainboard slots
  • DVI-I (Analog and Digital) Video Interface
  • Dual 10/100 Mbit Ethernet interfaces
  • Dual USB 2.0 Host interfaces
  • Dual USB 2.0 Device interfaces (one used as debug link)
  • Dual CAN bus interfaces
  • SPI and I²C controller interfaces, with on-board demonstration circuits and user pin headers
  • Dual serial UART (RS232)
  • Dual PS/2 Keyboard and Mouse interfaces
  • 16-bit User I/O
• Debug support over JTAG/Ethernet/USB/UART interfaces
• On-board oscillators
• Power, reset, clock and auxiliary circuits
• Rich software development infra-structure:
  • Snapgear linux-2.6 with SMP
  • RTEMS-4.10 , eCos-2.0 , Mentor Nucleus , VxWorks-6.x , LynxOs-2.0, ThreadX , Bare-C

Learn more about Customizable LEON4 Processor Systems