eASIC granted 11th patent for its configurable logic technology
December 15, 2004
San Jose, California, December 15, 2004 — eASIC® Corporation, a provider of Configurable Logic and Structured ASIC products, today announced that the company was granted an additional patent for its breakthrough technology. The patent entitled “Customizable and programmable cell array” (6,819,136), issued on November 16, 2004 by the United States Patent and Trademark Office, is a continuation of a previous patent (6,756,811) granted to eASIC in the area of chip customization. This patent protects the company’s unique configurable logic technology, which utilizes electrical programmable cells connected with lithography-defined custom interconnections. The patent also protects the use of a coarse-grain array fabric, where each cell comprises of flip-flops with some fine grain functions such as inverters or multiplexers used as logic gates.
eASIC’s patent portfolio protects the company’s Configurable Logic and Structured ASIC products from competing technologies attempting to use similar techniques to address today’s deep submicron design issues. However, eASIC is the only company who successfully integrated in one fabric FPGA-like logic programmability (SRAM-LUT) combined with segmented standard metal routing, customized by a single via-layer. This unique technology allows eASIC to offer fast-turn Structured ASIC products without NRE (Non Recurring Engineering) cost, by using efficiently existing maskless customization technique of Direct-Write eBeam.
“eASIC has been investing in developing a strong patent portfolio, seeking to grow its business through innovative technology and strategic alliances, focusing on critical market needs,” said Zvi Or-Bach, eASIC Founder and CEO. “Our Structured eASIC offers affordable design and fabrication costs, enabling our customers to easily implement their innovative applications in silicon. eASIC’s strategy is to secure a broad patent portfolio while joining forces with industry leaders to co-develop and market a complete solution, based on our breakthrough technology. This business approach is aimed at making the Structure eASIC available to customers through multiple sources, reducing risk and allowing diversified offerings by leveraging the partners’ core advantages.”
Innovative Configurable Logic Technology
eASIC has a unique Configurable Logic technology implemented in its Structured eASIC products. The patented architecture consists of SRAM-based logic cells and flip-flops that are interconnected by a segmented wiring grid utilizing upper metal layers. The logic cells programming is done similarly to an FPGA, by loading a bit-stream to program the LUTs (Look-up-Tables) and initialize the flip-flops after powering up the device. The routing and interconnection is done similar to other ASICs, but utilizes just a single via-layer for customization. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and a single custom Via-mask for customizing the routing. Moreover, the single mask can be eliminated for prototyping and low-volume by using Direct-write eBeam as maskless lithography. This is made possible because single via-customization is a perfect fit for Direct-write eBeam lithography. Hence, eASIC’s use of maskless lithography removes the customization tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-Free customized ASIC devices.
eASIC® has developed a breakthrough Configurable Logic technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. Its Structured eASIC architecture enables rapid and low-cost ASIC and SoC (System-on-Chip) designs by innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.
eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express.
Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201
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