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eASIC Introduces Configurable Logic Core for Platform-Based Designs to Enable Flexibility and Accelerated Time-to-Market

September 25, 2000



Embedded Systems Conference, San Jose, Calif., September 25, 2000 — eASIC® Corporation today introduced the eASICore™, a high performance and high-density configurable logic core aimed at accelerating the development cycle and supporting derivatives for platform-based designs and System-on-Chip (SoC). The eASICore was developed to allow rapid response to market and spec changes while maintaining the SoC price and performance objectives, thus helping the customer gain competitive advantage. Moreover, the eASICore has Standard Cell compatible performance and yet delivers the benefits of fast-turnaround configurable core in a cost saving approach.

“A recent research study that we have conducted on Embedded Configurable Logic, indicates that there is a major need in the market for increased configurability and flexibility at the device level to support continually changing and evolving system applications requirements,” said Jerry Worchel, President of inSearch Research (Phoenix). “The main barriers to this approach are the risks/costs associated with silicon area, performance, and/or process as related to the implementation of embedded configurable logic. It seams that eASIC is challenging this issue by offering a viable solution that addresses those concerns.”

Derived from its unique technology and architecture, the eASICore provides designers with a flexible and friendly design environment together with the means of getting first to market. The eASICore is ideally suited for use in platform-based designs. A chip with custom built-in processors, bus, an external interface and eASICore can be easily customized for any specific application.

“The need for this type of solution is becoming crucial, as the cost of semiconductor tooling is increasing dramatically with the introduction of smaller process geometries,” said Zvi Or-Bach eASIC President and CEO. “As tooling cost approaches $1 million it is imperative to use configurable logic to extend the design life-cycle and enable its re-usage as market requirements change. Additionally, with today’s complex electronics design, multiple iterations are often required for either fixing bugs or creating design revisions and derivatives, and in this reality, both the time-to-market and the NRE spending objectives are becoming a greater challenge. This is where the eASICore is of great benefit for the SoC designer.”

The eASICore™ Technology

The eASICore architecture is based on proprietary technology that provides an efficient solution for embedding configurable logic blocks in a fast, easy to implement and cost-effective method. This technology is rooted in a breakthrough concept of combining an SRAM Look-Up-Table cell with metal mask programmable interconnection. This combination allows delivering close to Standard Cell performance and density together with FPGA time-to-market and ease-of-design. Additionally, the eASIC technology addresses the issues of huge silicon area and circuit delay resulted from the programmable routing in existing FPGA devices. The eASICore technology takes advantage of the already proven Look-Up-Table approach for logic implementation, while avoiding the deficiencies of SRAM programmable routing. This is made possible since the routing of the eASICore is performed through metal-to-metal interconnection, which utilizes a much smaller silicon area and reduces the SoC production cost. Furthermore, the resulting delay of the eASICore routing is significantly (10 to 100 times) lower compared to SRAM controlled pass transistor devices and therefore the eASICore performance is similar to Standard Cell.

The eASICore™ Features

The eASICore can be ported across conventional silicon fabrication processes and therefore is flexible for use at various target foundries.

Each eASICore is 25K gate module, about 1mm sq.

Configurable as:

High logic density of ~30,000gate/mm2
Dual Port SRAM at 40K bit/mm2

As low as 7 day customization turnaround time
NRE cost of one to three masks (instead of ~30 masks used for Standard Cell customization)
Performance: compatible with Standard Cell, system clock speed of over 500 MHz
Design Friendly:

Built-in very low-skew, low noise, clock-tree.
Built-in complete scan test chain.
Built-in support for Post Placement drive Optimization.

Debugging Friendly Easy reload of Look-Up-Table for debugging purpose.

Full observability by using scan-chain

SoC Friendly

Multiple cores can be tiled and integrated to build
the required size of programmable logic.
Availability

The eASICore was designed and implemented in 0.18mm, 6 metal process. It can be implemented into silicon today by chip developers who utilize TSMC’s or UMC’s 0.18mm process technology.

For a limited time there will be no licensing fee for using the eASICore. The royalties at the production stage will be determined per customer design, depending on the expected volume and the number of eASICores used.

About eASIC

eASIC Corporation is pioneering a breakthrough approach of embedded configurable ASIC cores for System-on-Chip designs. This configurable ASIC core, called eASICore, offers high performance and density with ease-of-design, rapid time-to-market and low design development cost. eASIC Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania.

Contact

Jasbinder (Jazz) Bhoot
Senior Director, Marketing
jazz@eASIC.com
Tel: (408) 855-3028
www.eASIC.com