eASIC selects silicon canvas laker for structured ASIC designs
October 18, 2006
SAN JOSE, Calif. – October 18, 2006 -Silicon Canvas, Inc. today announced that eASIC, a San Jose California based Programmable ASIC company, has selected Silicon Canvas’ Laker Schematic Entry and Layout tools as part of the design and development flow for its next generation Structured ASIC fabric. The company will use Laker in its post Place & Route flow to view and fix DRC and LVS violations as well as for the design of its programmable IP core and configurable I/Os. This will help to achieve design success while reducing time-to-market on these very complex integrated circuits.
“Silicon Canvas’ Laker schematic and layout tools offer unique features and capabilities that allowed us to quickly and easily establish a schematic-driven layout flow,” said Jonathan Park, Vice President of Hardware Engineering at eASIC Corporation. “Our evaluation of the Laker products demonstrated that they offer a comprehensive solution that meets the challenges of our advanced process ASIC designs. “
“We are very excited to have been selected by eASIC for their advanced process designs,” said Mike Hartwell, VP of Operations for Silicon Canvas. “eASIC has put together a talented team of industry veterans who are committed to demonstrating that their Programmable Structured ASICs are a viable, lower cost, higher performance alternative to existing ASIC or FPGA models”.
The Laker design platform addresses the needs of today’s and tomorrow’s analog, mixed signal and large, complex IC, ASIC, and SoC designs. Laker has long been a recognized reference standard for full custom layout solutions, with more than 200 companies worldwide using it to deliver more than 2,300 successful chip tape outs. Built-in Controllable Automation Technology on top of a unified database system delivers a streamlined design work flow, from schematic to layout realization. Its patented Magic Cell, Rule-Driven, and Controllable Automation Technology conservatively deliver 6X productivity gains over existing methodologies.
About Silicon Canvas
Silicon Canvas, Inc., a privately held California corporation, was founded in 2001 by Dr. Hau-Yung Chen and other EDA veterans with combined 50+ years of custom design and EDA experience. Silicon Canvas is the technology leader for full custom design solutions. The company offers the Laker suite of tools – a completely new technology founded on best practices in computer software engineering with a clear focus on nanometer design requirements for analog, mixed signal, large complex IC’s, ASSP, SoC, test key designs and flat panel layout. Silicon Canvas’ toolsets bring more automation and higher performance capabilities to any design project that requires a more effective full custom layout solution. Customer applications include processors, computing systems, networking, telecommunication, and graphics ICs.
eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices and Configurable Logic IP aimed at dramatically reducing the overall fabrication cost and time of customized semiconductor chips. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology of FPGA-like programmable logic coupled with ASIC-like Via-layer customizable routing. This innovative fabric efficiently employs mask-less customization with Direct-write e-Beam, and thus allows eASIC to offer NRE-free Structured ASICs.
Founded in 1999, eASIC Corporation is privately held, headquartered in Santa Clara, California. Investors include Vinod Khosla, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, and Evergreen Partners. www.eASIC.com