eASIC’s first configurable logic core proven on UMC’s 0.18
May 8, 2001
eASICore® test chips offer high performance and high density
San Jose, California, May 8, 2001 — eASIC® Corporation, the technology innovator of configurable logic IP cores, today announced its eASICore® has been successfully proven in silicon, in the form of test chips, on UMC’s 0.18 micron, 6 metal-layer process. The initial manufacturing results show the eASICore® delivers both high performance and high density. Fabless companies as well as Integrated Device Manufacturers, that use UMC’s foundry services, can now have greater confidence when integrating the configurable embedded logic core, as it is proven in silicon.
“ASIC and System-on-Chip deep-submicron designers can now use, with minimal risk, our configurable logic core, that helps in the tedious task of debugging and allows for accelerating product derivatives,” stated Zvi Or-Bach eASIC® President and CEO. “eASIC provides designers with a cost-saving technological advancement, enabling them to reduce time-to-market and achieve a significant competitive advantage. The need for such a solution will become more and more critical, as each new process geometry will require seven-digit expense for tooling and first proof in silicon. Now proven in UMC silicon, eASICore®, can be immediately implemented as an embedded configurable logic or memory IP core within various SoCs applications such as communications and networking.”
The eASIC® core is now characterized at the silver level (Hardcore available, silicon verified) and will be represented in UMC’s Gold IP catalog. Jim Ballingall, UMC’s vice president of worldwide marketing said, “We are committed to helping designers and system developers overcome system-on-chip (SOC) and time-to-market hurdles by offering them access to third-party, proven IP blocks that can be readily integrated into their designs. The eASICore® should make a nice addition to our catalog as it delivers the cost-performance and design flexibility that many designers are seeking.
The eASICore’s architecture is based on proprietary technology that provides an efficient solution for embedding configurable logic blocks in a fast, easy to implement and cost-effective method.
eASICore® fabrication is done in conventional semiconductor process, but due to its proprietary technology, the eASICore® enables to significantly reduce the number of mask-sets used for programming. This eventually translates into major time and cost savings.
This technology is rooted in a breakthrough concept of combining an SRAM Look-Up-Table cell with metal mask programmable interconnection. This combination allows delivering close to Standard Cell’s performance and density together with FPGA’s time-to-market and
Additionally, the eASIC® technology addresses the issues of huge silicon area and circuit delay resulted from the programmable routing in existing FPGA solutions.
eASICore’s technology takes advantage of the already proven Look-Up-Table approach for logic implementation, while avoiding the deficiencies of SRAM programmable routing. This is achieved as a result of the metal-to-metal interconnection, which enables utilizing a much smaller silicon area (compared to other programmable logic offerings), resulting in a reduced production cost. Furthermore, the delay of the eASICore® routing is significantly (10 to 100 times) lower compared to SRAM controlled pass transistor devices and therefore the eASICore® performance is similar to Standard Cell.
The eASICore® and the supporting EDA tools are available today for implementation in silicon by chip developers that use UMC’s 0.18µm process technology.
eASIC Corporation is pioneering a breakthrough approach of embedded configurable ASIC cores for System-on-Chip designs. This configurable ASIC core, called eASICore®, offers high performance and density with ease-of-design, rapid time-to-market and low design development cost.
eASIC® Corporation is a privately held company based in San Jose, California. Part of its R&D activity is performed by its wholly owned design subsidiary in Romania. www.eASIC.com
As UMC’s IP partner, eASIC will participate in UMC’s Technology Forum 2001, being held in Santa Clara Convention Center on May 11, 2001.
Contact: Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201
Tel: (408) 264-7128