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eASIC’s innovative structured ASIC selected as designvision award finalist

January 20, 2005



(The industry recognizes the innovation embodied in eASIC’s configurable logic product – Structured eASIC)

San Jose, California, January 20, 2005 — eASIC® Corporation, a provider of Configurable Logic and Structured ASIC products, today announced that its Structured eASIC product was selected as a DesignVision Award finalist by The International Engineering Consortium (IEC). The Structured eASIC was selected for the category of “Structured/Platform ASIC, FPGA, and PLD Design Tools”. The inaugural DesignVision Award recognizes companies for recent products and services that have added a new dimension to the electronic design industry and to the society as a whole. The award ceremony will be held at the DesignCon conference in Santa Clara, Calif. on February 1, 2005. Award winners will be announced at the ceremony.

“The eASIC configurable logic technology moves the industry into a new era of ‘many ASIC designs per engineer’ from where it stands today as ‘many engineers per design’,” said Zvi Or-Bach, eASIC Founder and CEO. “We believe that the productivity and cost challenges facing the custom logic industry and slowing innovation are overcome by our unique solution and family of products. We are very proud that the users and industry experts have recognized the innovation and capabilities of this technology. The reality of designing millions of ASIC gates on a laptop by one engineer and receiving prototypes two weeks from fixing the RTL, all for zero dollars upfront is now upon us.”

Innovative Configurable Logic Technology – Structured eASIC

eASIC has a unique Configurable Logic technology implemented in its Structured eASIC products. The patented architecture consists of SRAM-based logic cells and flip-flops that are interconnected by a segmented wiring grid utilizing upper metal layers. The logic cells programming is done similarly to an FPGA, by loading a bit-stream to program the LUTs (Look-up-Tables) and initialize the flip-flops after powering up the device. The routing and interconnection is performed similar to other ASICs, but utilizes just a single via-layer for customization. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and a single custom Via-mask for customizing the routing. Moreover, the single mask can be eliminated for prototyping and low-volume by using Direct-write eBeam. Hence, eASIC’s use of maskless lithography removes the customization tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-Free customized ASIC devices with densities, power and performance akin to a standard cell ASIC.

About eASIC

eASIC® has developed a breakthrough Configurable Logic technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. Its Structured eASIC architecture enables rapid and low-cost ASIC and SoC (System-on-Chip) designs by innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.

eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express.
www.eASIC.com

Contact

eASIC Corporation
Jasbinder (Jazz) Bhoot
Senior Director, Marketing
Tel: (408) 855-3028
Fax: (408) 855-9201
jazz@easic.com

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2005-01-20