eASIC Corporation

eASIC Enables 3X Increase in Energy Efficiency for Astrophysical Simulation Supercomputer

eASIC — Wed, 02 May 2012 12:50:24 +0000

Santa Clara, CA – May 2nd, 2012 – eASIC Corporation, a provider of NEW ASIC devices, today announced that Tokyo Institute of Technology, in collaboration with Hitotsubashi University, has successfully demonstrated a 3X increase in energy efficiency for a green supercomputer used for performing astronomical simulations. By leveraging eASIC´s low power Nextreme-2 NEW ASIC devices, Tokyo Institute of Technology was able to achieve an energy efficiency ratio of 6.5 GFLOPS/Watt for its GRAPE-8 supercomputer.

The key component in achieving the highest energy efficiency ratio for the GRAPE-8 system is the use of eASIC´s Nextreme-2 NEW ASIC devices, which are commonly used for replacing FPGAs for high volume and power sensitive applications. Manufactured using a low-power 45nm LP process, and employing single via programming which eliminates the need for power hungry SRAMs that FPGAs require for programming look-up tables and routing, eASIC devices typically enable FPGA users to achieve up to 80% lower power consumption. eASIC´s unique GreenPowerVia technology also enables users to completely turn off any logic and memories that are unused in a design.

"eASIC´s devices have enabled us to take a giant step forward in resolving the power issue with next generation supercomputers," commented Junichiro Makino, Professor at Tokyo Institute of Technology Graduate School of Science and Engineering. "Standard cell ASIC was prohibitively expensive and FPGA power consumption simply could not allow us to beat the previous record of 2.1GFLOPS/Watt which was held by IBM´s BG/Q green supercomputer. eASIC´s NEW ASIC allowed us to achieve a new record of 6.5 GFLOPS/Watt," added Makino.

"This great accomplishment by Junichiro Makino and his team is testament to the innovative power saving technology eASIC has developed," said Jasbinder Bhoot, Vice President of Marketing, eASIC Corporation. "The energy efficiency numbers they are demonstrating are very impressive. In many industries ranging from wireless infrastructure to enterprise storage, we are helping customers overcome the power problems caused by FPGAs. When low-power consumption is paramount, like Tokyo Institute of Technology´s GRAPE-8 processor, eASIC´s Nextreme-2 devices are the ideal choice," added Bhoot.

About eASIC

eASIC is a fabless semiconductor company offering breakthrough NEW ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer a new generation of ASICs with significantly lower up-front costs than traditional ASICs.

Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information on eASIC please visit www.easic.com.

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@eASIC.com

eASIC Surpasses 3 Million Chips Shipped and is set to Double This in 2012

eASIC — Mon, 27 Feb 2012 13:46:41 +0000

Santa Clara, CA – February 27, 2012 – eASIC Corporation, a provider of NEW ASIC devices, today announced that it has shipped in excess of three million chips and achieving this shipment milestone firmly solidifies eASIC’s position as a high volume supplier of custom integrated circuits. eASIC expects to be at more than double that number of shipments by the end of 2012.

“eASIC’s disruptive NEW ASIC devices are enabling OEMs and ASSP companies to get to market up to six months earlier than with traditional cell-based technology,” commented Jasbinder Bhoot, eASIC VP Marketing. “When our customers look at the overwhelmingly positive revenue impact of getting products into the market six months sooner, it’s a logical choice to choose eASIC NEW ASIC devices rather than use cell-based ASIC technology. With eASIC, designers benefit from a much simpler, much lower cost and significantly lower risk design flow than that of cell-based ASIC. Many typical ASIC tasks such as DFT insertion, clock tree synthesis and IR drop do not need to be performed. Placement and routing tools are also developed by eASIC. In addition, OEMs benefit from a much simpler manufacturing flow that only requires one single via mask for customizing the entire chip,” added Bhoot.

“As a fabless semiconductor company, eASIC has spent considerable effort in streamlining our supply chain and ISO certified processes in order to meet the stringent requirements of our broad Tier 1 OEM and ASSP customer-base,” said Ronnie Vasishta, eASIC President and CEO. “We are shipping devices into carrier grade wireless infrastructure applications, medical electronics, smart grid infrastructure and into consumer markets too. Some of these applications were traditionally served by FPGAs, while others by cell-based ASICs. What is crystal clear is that we are taking share away from both. FPGAs are hitting a power and performance wall in the new process nodes so a tipping point moving away from FPGA to a low cost ASIC solution is developing, while traditional cell-based ASICs just take too long to design and manufacture,” added Vasishta.

To learn more about eASIC products, visit www.easic.com.

About eASIC

Forward Looking Statements

This press release contains forward-looking statements, including, without limitation, statements related to eASIC’s future sales and distribution of its NEW ASIC devices. Works such as “expects” and similar expressions are intended to identify forward-looking statements. These forward-looking statements are based upon eASIC’s current expectations. Forward-looking statements involve risks and uncertainties. The company’s actual results and the timing of events could differ materially from those anticipated in such forward-looking statements as a result of these risks and uncertainties, which include, without limitation, economic conditions, customer business environment and inventory levels, government and technological factors outside of our control, adoption and roll-out of products, risks related to ability to capitalize on growth opportunities and markets, risks related to our ability to manage our growth and other risks that may cause our business, industry, strategy or actual results to differ materially from the forward-looking statements. eASIC expressly disclaims any obligation or undertaking to release publicly any updates or revisions to any forward-looking statements contained herein.

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@eASIC.com

eASIC Grows 2011 Revenue by 80%

eASIC — Mon, 30 Jan 2012 13:50:33 +0000

Santa Clara, CA – January 30, 2012 – eASIC Corporation, a provider of NEW ASIC devices, today announced 80% growth in sales revenue from calendar year 2010 to 2011. The majority of the revenue in 2011 was split between wireless infrastructure and storage markets. However, other applications also contributed to the revenue. At the end of 2011 eASIC had completed 170 tape-outs and had delivered 167 prototypes. In addition, 66% of the revenue was derived from shipping new products, namely, 45nm Nextreme-2 NEW ASIC production.

“eASIC’s low-NRE, fast-turn NEW ASIC devices are being used in a wide range of applications including 3G and 4G wireless base stations, wireless and optical backhaul, cloud computing with enterprise solid state storage, consumer hybrid SSD drives and medical ultrasound consoles,” said Jasbinder Bhoot, eASIC VP Marketing. “OEMs have been able to significantly reduce their total-cost-of-ownership by rapidly migrating to eASIC devices for volume production and hence limiting the use of expensive FPGAs to prototyping only. eASIC’s ability to also rapidly deliver low-cost, production devices at a fraction of the cost of cell-based ASIC, is enabling consumer electronics OEMs to fearlessly venture into new untapped markets, with significantly lower cost and lower risk.”

“2011 has been a phenomenal year of growth for eASIC,” commented Ronnie Vasishta, eASIC President and CEO. “Unlike much of the semiconductor industry which saw a revenue decline in wireless infrastructure, we were able to grow substantially and expand our customer base. What’s particularly exciting for us is our growing portfolio of Tier-one OEM customers, as this is a strong testament that our core value proposition of affordable mass customization is hitting resonance.”

To learn more about eASIC’s Nextreme-2 NEW ASICs and easicopy™ cell-based ASIC products, visit www.easic.com.

About eASIC

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@eASIC.com

eASIC Appoints Industry Veteran, Brian McDonald as Chief Financial Officer

eASIC — Thu, 18 Aug 2011 13:02:20 +0000

Santa Clara, CA, – August 18, 2011 – eASIC Corporation, a provider of NEW ASIC devices, today announced that Brian McDonald has been appointed as Chief Financial Officer (CFO) and Vice President of Finance. As a key member of eASIC´s executive team, McDonald will assume a strategic role in the company that involves spearheading future growth initiatives in addition to managing the company’s financial functions. McDonald will report to eASIC´s President and CEO, Ronnie Vasishta.

"I am delighted Brian has decided to join the eASIC team. His experience and understanding of the important relationships between finance and the rest of the business is extremely important as we approach the next very exciting phases of our growth," said Vasishta. "He brings a solid proven track record of success in taking companies through the stages that eASIC is now facing. He is a well-respected financial executive in the semiconductor industry and we will benefit greatly from this experience."

Brian McDonald has over 30 years of finance experience with high technology companies. Prior to joining eASIC, Brian was the Chief Financial Officer, Sr. VP of Finance and Secretary at Advanced Analogic Technologies (AATI) a public silicon valley company. Brian was instrumental in taking AATI successfully through the IPO process in 2005. Prior to AATI Brian has held senior financial positions at Monolithic Power Systems, Elantec Semiconductor, National Semiconductor, Mattson Technology, Micro Linear, and Read-Rite corporation.

"I am in awe at how the eASIC team has successfully executed and met stringent growth targets even within a very turbulent economy and has successfully acquired an impressive portfolio of tier one corporations as customers," said McDonald. "This solid base is a strong platform for the next phase of the company´s growth."

Brian holds a BS degree in Business Administration from Santa Clara University.

About eASIC

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@eASIC.com

IP Development HW Leader

eASIC — Mon, 20 Jun 2011 18:45:19 +0000

Title: IP Development HW Leader
Location: Santa Clara, USA
Job ID: US2011012

IP Development HW Leader

This position involves leading a team of HW IP developers in the creation of interface and logic fabric IP for eASIC structured ASIC devices. The position will involve active IP development as well as team leadership. Target markets are the communication and video sector with strong experience preferred in one of these target markets

Required Experience

Bachelors or Masters Degree
At least 5 years experience leading a team of people developing sophisticated IP (PCI Express Controllers, Interlaken MACs, VbyONETx/Rx, Ethernet MACs, DDR memory controllers for example) with proven successful field deployment.
At least 10 years experience developing IP for FPGAs, ASIC or Structured ASIC devices with proven success in field deployments.

Required Skills

excellent communication skills and leadership qualities
ability to successfully manage projects to a marketing requirements document and agreed upon schedule
knowledge of Verilog, UNIX scripting and C programming
Experience using one of the following simulation tools: VCS, Modelsim, Verilog XL
Demonstrable knowledge of successful testing strategies and testbench architectures
Strong knowledge of High speed transceiver technologies and proven experience developing IP using Transceivers.
Knowledge of IP limitations in relation to silicon I/O architecture and performance limitations
Willingness to work with teams in Europe and Malaysia

Qualified candidates should email their resumes and salary requirements to hr@eASIC.com. Please indicate the Job ID in the subject line of your email.

Principals only please

IP Developer

eASIC — Mon, 20 Jun 2011 18:44:16 +0000

Title: IP Developer
Location: Santa Clara, USA
Job ID: US2011011

Qualifications:

Principle design engineer with MS in Electrical Engineering/Computer Engineering and at least 10+ years of design experience and has successfully delivered complex designs to production.

Job Summary:

You will be involved in design and verification of 1G – 28G protocols including but not limited to PCIe Gen 3.0/2.0/1.0, Gigabit Ethernet, XAUI, CPRI, SRIO, 10G Base-R, Interlaken, etc. You will also need to perform frontend to backend tasks using semi-custom design flow including but not limited to design, floorplanning, verification, synthesis, timing closure, ECO, power analysis, etc. You will be involved in pre-silicon and post-silicon debug and support and you will work independently with local and global counterparts.

Description:

At least 5 years experience on digital protocol IP design for High Speed Serial protocols (such as PCI Express 2.0/2.1/3.0, Gigabit Ethernet, Interlaken, 10G Ethernet, CPRI, etc)
Experience must include architecture definition and IP development on Physical Coding Sublayer, Media Access Controller, Data Link and Transaction layer components
Experience in ASIC design methodology from front-end to back-end covering RTL Verilog/VHDL coding, Logic Verification (VMM/SystemVerilog is a plus), Synthesis, Floorplanning, Formal Verification, Static Timing Analysis. Experience in Place and Route is an added advantage
Provide Floorplaning Guidance & Review of critical layout designs
Work with our counterparts on many inter-dependent deliverables across geographical sites from various departments like Product Marketing, Test Development, Software Engineering, Product Engineering, Technology, Reliability, Applications, etc
Good communication and presentation in English is expected

Experience

BSEE/MSEE/PHD with minimum 10+ years of experience in high gate-count digital/mixed-signal IC design at 65nm or smaller technology with clock frequency > 400 MHz
Experience of entire design cycle from micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment – preferably for several products.
Strong language user in SystemVerilog, Verilog, Perl, Unix Shell
Experience in both RTL and gate level verification and debug
Experience in coverage based/random test environment and assertion generation
Experience in Cadence or Synopsys design environments, for example using NC-Verilog, RTL compiler, ETS is a plus
Design experience in 2 of following product areas
High speed serial link (PCI-E, SATA, 10G Ethernet, HDMI/Display Port, etc)
DDR2/DDR3 memory controller
High speed network or switching controller
PC chipset, North/South Bridge controller
Other multi-million gates digital/mix-signal design

Skills:

Define module level architecture specifications for next generation Mixed-Signal products
RTL code implementation using Verilog/SystemVerilog
Own pre-layout synthesis and timing closure using Cadence design environment
Work with backend engineer on post-layout timing closure
Work with verification engineering to debug test cases in RTL and Gate Level simulation environment. Define and generate assertion for his/her own module
Post-silicon debug and correlation

Qualified candidates should email their resumes and salary requirements to hr@eASIC.com. Please indicate the Job ID in the subject line of your email.

Principals only please

Sr Staff Signal Integrity Designer

eASIC — Mon, 20 Jun 2011 18:40:21 +0000

Title: Sr Staff Signal Integrity Designer
Location: Santa Clara, USA
Job ID: US2011013

Description

Senior Staff Signal Integrity Designer is to oversee both Signal and Power integrity and SerDes architecture effort for world-class highly flexible transceiver solutions for multiple eASIC platforms, supporting over 20 protocols with several customer applications. You will be involved in working the following set of protocols – PCIe Gen 3.0/2.0/1.0, Gigabit Ethernet, XAUI, CPRI, SRIO, 10G Base-R, Interlaken, etc.

The successful candidate should have an excellent track record in the following areas:

Signal integrity, channel modeling, and timing recovery
Running and developing communication system simulators
Writing specification for design teams.
Presenting design trade-off analyses and implementation recommendations with custom circuit designers

Job Requirements

BSEE or MSEE
Experience in both RTL and gate level verification and debug
5 or more years of hands on experience in design, characterization, debug of high Speed SERDES ranging from 1G to 13Gbps
10 or more years of architecture experience with high-speed communication systems
Experience with signal and Power integrity analysis
Experience with using and developing transceiver modeling, analysis, and characterization tools
Experience with lab equipment for high-speed digital systems
Excellent technical communication through presentations and documentation

Qualified candidates should email their resumes and salary requirements to hr@eASIC.com. Please indicate the Job ID in the subject line of your email.

Principals only please

Cisco Senior Vice President of Engineering Pankaj Patel Joins eASIC Board of Directors

daniel — Thu, 26 May 2011 08:54:30 +0000

Santa Clara, CA, May 26, 2011 – eASIC Corporation, a provider of NEW ASIC devices, today announced that Pankaj Patel, Cisco Senior Vice President of Engineering has joined eASIC’s Board of Directors.

“I am very excited to join eASIC’s Board of Directors. eASIC has a proven, disruptive technology that adds significant value to their customers by displacing power hungry and costly FPGAs or lowering the development cost of traditional ASICs,” said Pankaj Patel. “At a point when many companies in high growth markets are implementing cost reduction strategies to improve gross margins and competitiveness, eASIC is ideally positioned to have a dramatic impact in the custom logic arena.”

“We are very excited to have Pankaj join our Board of Directors,” said Ronnie Vasishta, President and CEO of eASIC. “As a seasoned senior executive, Pankaj brings a unique and valuable engineering, and business management expertise gained at a combination of highly successful small, medium and large enterprises. His experience in growing and scaling businesses will be immensely valuable to eASIC, as we expand our market footprint and continue our aggressive revenue ramp primarily from tier one wired, wireless and storage infrastructure customers.”

Patel’s role at Cisco encompasses development, strategy and execution of its $32 billion product portfolio, as well as go-to-market strategies and customer value propositions for its $10 billion Service Provider business. Prior to Cisco, Patel has held senior management positions at Apollo Computer/HP, Digital Equipment Corporation, Stratacom and Redback. From 1999 to 2003, Patel was Senior Vice President of Engineering at Redback Networks and responsible for all products at Redback Networks. Patel holds a master’s degree in electrical engineering from the University of Wisconsin-Madison and a bachelor’s degree in engineering from Birla Institute of Technology and Science in Pilani, India.

About eASIC Corporation

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@eASIC.com

Pankaj Patel, Senior Vice President of Engineering, Cisco Systems

daniel — Thu, 26 May 2011 08:51:42 +0000

I am very excited to join eASIC’s Board of Directors. eASIC has a proven, disruptive technology that adds significant value to their customers by displacing power hungry and costly FPGAs or lowering the development cost of traditional ASICs. At a point when many companies in high growth markets are implementing cost reduction strategies to improve gross margins and competitiveness, eASIC is ideally positioned to have a dramatic impact in the custom logic arena.

Kurt Richarz, Seagate Executive Vice President of Sales

eASIC — Wed, 25 May 2011 11:52:06 +0000

Seagate is delighted to have launched Momentus^®XT, the industry’s first solid state hybrid drive, using the easicopy ASIC Migration product. We were able to use Nextreme NEW ASICs to accelerate time-to-market of Momentus®XT. eASIC seamlessly migrated our design to easicopy™. We see easicopy™ as a natural extension to our value engineering programs as we take products from initial ramp through to very high volumes.

eASIC Announces easicopy™ ASIC

eASIC — Wed, 25 May 2011 11:49:46 +0000

New Product Mitigates Traditional Risks of Cell-based ASIC Design

Santa Clara, CA – May 25, 2011 – eASIC Corporation today announced the immediate availability of “easicopy™”, an ASIC migration product that provides custom chip designers with a simple, low-risk migration path from eASIC Nextreme and Nextreme-2 NEW ASICs to cell-based ASIC devices.The addition of easicopy™ enables OEMs to continue to innovate and quickly ramp to volume production using eASIC Nextreme series devices, and now migrate to lower cost easicopy™ cell-based ASIC when designs ramp to extremely high volumes.

OEMs typically engage in an easicopy™ design once their lower up-front cost Nexteme series design has been proven and is profitably ramping in production. eASIC engineers seamlessly migrate the Nextreme or Nextreme-2 design netlist to an easicopy™ solution taking care of arduous tasks such as DFT insertion, ATPG, I/O ring and power mesh design, clock tree synthesis, package design, routing, extraction, IR drop and formal verification. While eASIC engineers are migrating the design to easicopy™, OEMs continue to profitably ramp in production with the Nextreme series design, thereby mitigating overall design and production risks. Once the easicopy™ design is complete OEMs are able to switch production from their Nextreme or Nextreme-2 design to easicopy™ in order increase gross margins even further.

“Seagate is delighted to have launched Momentus®XT, the industry’s first solid state hybrid drive, using the easicopy ASIC Migration product,” said Kurt Richarz, Seagate executive vice president of sales. “We were able to use Nextreme NEW ASICs to accelerate time-to-market of Momentus®XT. eASIC seamlessly migrated our design to easicopy™. We see easicopy™ as a natural extension to our value engineering programs as we take products from initial ramp through to very high volumes.”

“We are seeing more customers who are successfully in volume production with their Nextreme series devices, wanting to ramp to very high volumes,” said Jasbinder Bhoot, Vice President of Worldwide Marketing, eASIC Corporation.“The combination of low-up front cost Nextreme series devices,and the lowest unit cost of easicopy™ solutions now gives customers the power to freely innovate and seamlessly ramp successful innovations from hundreds of thousands of units to millions of units, all with eASIC.”

About easicopy™

The easicopy™ ASIC migration product supports ASIC migrations from 90nm eASIC Nextreme and 45nm eASIC Nextreme-2 families to cell-based ASICs from foundries such as Fujitsu Semiconductor, GLOBAL FOUNDRIES and others. To learn more about easicopy™, visit www.eASIC.com

About eASIC

About Seagate

Seagate is the worldwide leader in hard disk devices and storage solutions. Learn more at http://www.seagate.com.

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com

embedded

eASIC Introduces 45nm ASIC Value Shuttle™ Program

eASIC — Tue, 07 Dec 2010 14:12:50 +0000

New Value Shuttle™ Delivers 45nm NEW ASIC Prototypes for $45K

Santa Clara, CA – December 7, 2010 – eASIC Corporation, a provider of NEW ASIC devices, today introduced a Value Shuttle™ program that lowers the entry cost for 45nm ASIC designs. The 45nm Value Shuttle™ enables designers to receive forty-five (45) eASIC Nextreme-2 NEW ASIC prototypes for only forty-five thousand dollars ($45K), a small fraction of the cost of competing ASIC solutions. Through reducing the cost, and hence development risk of ASIC design prototypes, the 45nm eASIC Value Shuttle™ enables designers to bring forward the transition point where designs switch from FPGA to ASIC.

In addition to allowing OEMs to quickly cost reduce FPGA designs, the 45nm Value Shuttle™ enables designers to inexpensively and quickly test new markets. Successful product innovations can be ramped to production at a much lower device cost than equivalent logic density FPGAs thereby enabling OEMs to ramp to profitability much sooner.

“We have streamlined our design flow to make transitions from FPGAs to eASIC Nextreme-2 NEW ASICs a simple process,” commented Jasbinder Bhoot, Vice President Marketing at eASIC Corporation. “After a number of successful 45nm designs many of which are in volume production, we are now lowering the cost of customization for 45nm ASICs even further. The eASIC Value Shuttle™ will enable designers to plan their FPGA cost reductions right from design start. This will start to reverse the trend in declining ASIC design starts and will enable customers to use ASICs rather than FPGAs even for moderate volume applications.”

The 45nm Value Shuttle™ is available immediately for all eASIC Nextreme-2 NEW ASIC designs. Typical users are in demanding end applications such as carrier class wireless, and wired infrastructure, medical equipment or many others where FPGAs are too expensive and/power hungry or replacing legacy cell-based ASICs that require additional functionality. $45K covers the cost of 45 NEW ASIC prototypes but does not include software tools and licensing, design services, where applicable, and production. ASIC and FPGA designers are able to quickly convert their designs to eASIC Nextreme-2 using eASIC’s industry proven eTools 8.2 Design Suite. A free 30 day evaluation of the eTools 8.2 Design Suite is available at www.easic.com.

About eASIC

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com

embedded

eASIC and Radiocomp Deliver Low Power 6G CPRI v4.1 REC Solution

eASIC — Tue, 09 Nov 2010 03:00:57 +0000

Power Consumption of CPRI-based Designs Reduced by up to 80%, With exceptionally High Signal Integrity Compared to FPGA Implementations

Santa Clara, CA, November 9, 2010 — eASIC Corporation, a supplier of NEW ASICs and Radiocomp, a leading provider of modular RF systems and components for mobile and wireless infrastructure networks, today announced the immediate availability of a low power Common Public Radio Interface (CPRI) v4.1 solution for Radio Equipment Controller (REC) equipment. Using the low power transceivers on eASIC Nextreme-2T NEW ASICs, and the industry proven CPRI v4.1 REC IP core from Radiocomp, the solution consumes only 190 mW per channel at 6.144 Gbps. The combination of CPRI v4.1 IP and eASIC Nextreme-2T NEW ASICs enables base-station baseband module suppliers to accelerate cost reductions of FPGA-based designs and at the same time decrease power consumption by up to 80%.

CPRI is the most widely deployed interface between baseband and radio sections of a wireless base station and has traditionally been implemented using expensive and high power consumption FPGAs. The availability of the eASIC CPRI REC solution allows FPGA designers to engage in cost and power reduction efforts much sooner, and at a fraction of the development cost for cell-based ASICs.

“We are delighted that eASIC has selected our CPRI v4.1 REC IP technology to expand its wireless portfolio. Our implementation of the core onto eASIC Nextreme-2T shows exceptionally high signal integrity when compared to some FPGA-based solutions. We believe that this will enable base station vendors to quickly design eASIC Nextreme-2T-based CPRI REC solutions at a lower system cost and with reduced power consumption, much faster than before,” said Christian Lanzani, Senior Product Manager in Radiocomp ApS.

“We are seeing very little innovation from FPGA vendors to help customers reduce cost and power in base station designs,” commented Jasbinder Bhoot, eASIC Vice President Worldwide Marketing. “The inclusion of the CPRI REC IP to our silicon proven serdes capability means that at last radio base station designers can have a lower cost and lower power alternative to FPGAs. In addition, the signal integrity of the eASIC solution also demonstrates that eASIC’s Nextreme-2T transceiver is fully compliant with all CPRI V4.1 specifications.” added Bhoot.

The Radiocomp CPRI v4.1 core has already been verified in both FPGAs and eASIC devices and features:

Built-in support for CPRI v4.1 REC and backwards compatible mapping methods
Programmable Line rates up to 6.144 Gbps.
Up to 32 antenna carriers per IP core
Integrated HDLC and 10/100 Ethernet MAC controllers or external MII interface
Portable HDL code for easy migration from FPGAs to eASIC

About eASIC Corporation

About Radiocomp

Radiocomp (acquired by MTI Group in Oct. 2010) is a global pioneer in the development and manufacture of state-of-the-art, fully software-configurable and remotely tunable radio head products and radio components. The company is a leading provider of modular RF systems and components for existing and next generation mobile infrastructure networks. Radiocomp offers expertise in research and development as well as in the application of RRH to WiMax/3GPP LTE mobile technologies for the development of custom design solutions. Following the acquisition by MTI Group – which is already internationally recognized as a global leader in RF and microwave products – the two companies have combined hardware and software R&D capabilities, facilitating a business expansion into the 4G market. For more information please visit www.radiocomp.com and www.mti.com.tw.

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com

embedded

eASIC Enables Early Rollout of On-Ramp Wireless’ eNODE Solutions

eASIC — Tue, 05 Oct 2010 16:35:14 +0000

eASIC Nextreme NEW ASICs Accelerate Adoption of Wireless Solutions for Smart Grid, Remote Sensing and Location Tracking Systems

SANTA CLARA, CA, – October 5, 2010 – eASIC Corporation, a provider of NEW ASIC devices, today announced that On-Ramp Wireless, Inc., a provider of low-power, wide area scalable wireless networking systems successfully rolled out its eNode Wireless modules six months ahead of schedule. Its fast-turnaround was facilitated by eASIC’s Nextreme NEW ASICs, which is a part of the eNODE baseband processing engine. eNODE wireless modules are used in wide area, low power and low data rate applications such as sensor monitoring, utility distribution automation, smart metering, and location tracking, to name some examples.

eASIC Nextreme NEW ASICs provide designers with a unique platform for reducing the time (and development cost) of custom chip designs, compared to traditional cell-based ASICs. Designers are able to implement designs and receive fully tested chips back in a fraction of the time, thus enabling early customer traction and market penetration. In addition to enabling fast market access, eASIC’s patented technology enables device manufacturing to start ahead of design completion. Wafers can be staged and customized late in the manufacturing cycle for unique customer designs enabling OEMs to receive tested ASIC devices in only six weeks after design tape-out.

“eASIC’s devices provided us with an inexpensive vehicle to get to market and ramp up production quickly,” commented Jonas Olsen, Vice President of Marketing at On-Ramp Wireless. “As we target many markets that are still emerging, development cost, development time, and flexibility to innovate and change quickly are critical.”

Built on On-Ramp’s Ultra-Link Processing™ (ULP) technology, the eNode is the first wireless module to provide metro-scale wireless networking in unlicensed ISM-bands. ULP also enables the system to provide a significant increase in network capacity, which substantially lowers network infrastructure and cost.

“On-Ramp’s innovative ULP signal processing technology is in high demand for a wide variety of wireless systems used for control and monitoring,” said Jasbinder Bhoot, Vice President of Marketing, eASIC Corporation. “To meet their customer demand in Smart Grid, industrial sensing and location tracking requires the ability to quickly develop cost effective solutions. eASIC’s Nextreme devices are the ideal choice when time to market and low-cost are paramount.”

About eASIC

About On-Ramp Wireless

On-Ramp Wireless has developed the first wireless system purpose-built to efficiently connect billions of hard-to-reach devices in metro scale and other challenging environments. On-Ramp’s field-proven Ultra-Link Processing™ system enables low-power monitoring and control applications within Smart Grid, water efficiency, industrial sensing, and location tracking. Operating in un-licensed spectrum, our signal processing innovation finds weak signals even in high noise environments, yielding extreme coverage, immunity to high interference, and significantly lowers cost. For more information, visit www.onrampwireless.com.

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com

embedded

eASIC Appoints Richard Heye as Chief Operating Officer

eASIC — Tue, 15 Jun 2010 06:00:01 +0000

Seasoned Semiconductor Industry Executive Joins eASIC to Manage the Company Operations Ramp Through the Next Phase of Growth Acceleration

Santa Clara, CA – June 15, 2010 – eASIC Corporation, a provider of NEW ASIC devices, today announced that Richard Heye has been appointed as Chief Operating Officer (COO). Heye brings 30 years of executive management, engineering and operations experience from within the semiconductor industry. Heye is chartered with spearheading eASIC’s engineering development of, as well as, growing operations to meet the rapid customer ramp. Heye will report directly to CEO, Ronnie Vasishta.

“We look forward to the significant expansion of skills and bandwidth that Richard brings to eASIC which is going to be invaluable as move into the next phase of the company growth service many multinational multi-billion dollar customers,” commented Ronnie Vasishta, President and Chief Executive Officer at eASIC. “Richard’s operations experience is valuable as we now see a significant ramp in production on 90nm and 45nm. Also Richard’s engineering background will be essential in the release of our 28nm product.”

Previously, Heye served as the Senior Vice President of the SSD Division at SanDisk. Prior to SanDisk, Heye served as the General Manager of the Discrete Graphics Desk Top Business Unit at ATI Technologies. Previously Heye held a series of engineering, infrastructure creation and general management roles at Advanced Micro Devices (AMD), where he is credited with establishing a solid desktop, mobile and server infrastructure in the marketplace for Athlon FX, Athlon 64, and Opteron. Heye’s career also includes Director of Desktop Macintosh products at Apple Computer. Heye began his career as a designer and engineering manager within the Digital Equipment Corp. microprocessor group.

“I am excited to be joining eASIC during this period of expansive revenue growth” commented Richard Heye, eASIC COO. “I look forward to supplying the best family of products and development tools in the industry to solve our customers ever increasing challenges.”

Heye earned Bachelor Degrees in electrical engineering and computer science as well as a Masters in Computer Science from Washington University in St. Louis. He holds 3 patents.

About eASIC

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com

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Mr. Dai Vu, Director of Virtualization Solutions Marketing, Microsoft Corp.

eASIC — Thu, 13 May 2010 06:00:51 +0000

By working with eASIC’s Nextreme NEW ASIC, we were able to develop a reference design for RemoteFX hardware solutions that is low in power consumption as well as low in up-front development cost. “We see eASIC’s Nextreme as a platform well suited for our efforts to quickly validate new technologies, but also as a catalyst in enabling our RemoteFX partner ecosystem to ramp up their solutions to market readiness.

eASIC Nextreme Used for Hardware Validation of Microsoft RemoteFX Technology

eASIC — Thu, 13 May 2010 06:00:16 +0000

Companies Work Together to Accelerate Market Adoption of Desktop Virtualization

Santa Clara, CA – May 13, 2010 – eASIC Corporation today announced that it is working with Microsoft Corp. on using eASIC’s Nextreme NEW ASICs to create a hardware implementation of the Microsoft RemoteFXTM technology, which was announced two months ago. eASIC’s Nextreme product has been able to quickly validate the Microsoft RemoteFX technology in silicon and to attract a growing ecosystem of companies interested in developing eASIC-based solutions that accelerate the adoption of remote and shared resource computing applications.

Microsoft RemoteFX promises to deliver a media-rich Windows desktop experience to all types of remote client devices including low-cost thin clients. Microsoft RemoteFX is a new platform technology in Windows Server 2008 R2 SP1 that leverages hardware acceleration on the host to create a rich user experience for a centralized desktop computing environment. With Microsoft RemoteFX, screen images are rendered on the host, lessening the graphics requirements on the remote client.

“By working with eASIC’s Nextreme NEW ASIC, we were able to develop a reference design for RemoteFX hardware solutions that is low in power consumption as well as low in up-front development cost,” said Dai Vu, director of Virtualization Solutions Marketing, Microsoft Corp. “We see eASIC’s Nextreme as a platform well suited for our efforts to quickly validate new technologies, but also as a catalyst in enabling our RemoteFX partner ecosystem to ramp up their solutions to market readiness.”

“Desktop virtualization is a growing trend among IT professionals aiming at centrally delivering and managing a modern desktop from the datacenter, and we are delighted to be collaborating with Microsoft in making this initiative a reality,” said Jasbinder Bhoot, Vice President of Worldwide Marketing, at eASIC Corporation. “Microsoft has over a decade of experience in enabling centralized desktop solutions, and we are convinced that customers will embrace Microsoft RemoteFX as a key ingredient of flexible desktop virtualization solutions that provide a rich, local-like user experience for server-hosted desktops and applications,” added Bhoot.

For more information on eASIC’s Nextreme NEW ASIC family, visit www.easic.com

About eASIC

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com

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eASIC eTools 8.1 Design Suite Reduces Design Time by 40%

eASIC — Wed, 05 May 2010 07:00:58 +0000

New eTools 8.1 Enables Designers to Achieve up to 30% Higher Performance in 40% Less Time

Santa Clara, CA – May 5, 2010 – eASIC Corporation, a provider of NEW ASIC devices, today announced the immediate availability of its eTools 8.1 Design Suite for implementing 45nm eASIC Nextreme-2 designs. The eTools 8.1 tool suite delivers a robust ASIC grade design flow with the simplicity and ease of design that is normally associated with FPGA design tools. New features and enhancements in eTools 8.1 enable designers to reduce overall design time by up to 40% while increasing design performance by up to 30% compared to the previous eTools 8.0 suite.

New features and utilities within eTools 8.1 focus on reducing design conversion and implementation time, while enhancing the overall quality of results. The rich tool suite now includes a complete floorplanner with interactive regioning capability, and a powerful new detailed placer based on a set of new advanced proprietary algorithms that are optimized for eASIC’s single via customization logic architecture. Both utilities also combine to facilitate rapid timing closure on complex NEW ASIC designs. eTools 8.1 also includes unique capabilities that enable rapid RTL design conversion from traditional design platforms such as FPGA and ASIC.

“An increasing number of FPGA designers are using our technology to reduce the cost and power of their designs, but they want design time to be quick once they have finalized their FPGA design. With eTools 8.1 we focused on speeding up the key steps in the design process. Initial feedback indicates that we have made significant strides to help designers quickly convert and implement their designs onto eASIC Nextreme-2 and achieve their desired performance”, said Dr. Ranko Scepanovic, Senior Vice President, Software and Advanced Technology at eASIC Corporation.

Unlike traditional standard cell ASIC flows, the eTools 8.1 design flow enables designers to focus their efforts on achieving the desired functionality and timing of their design, and not on arduous complex tasks such as power mesh design, signal integrity, test insertion, DFM (design for manufacture) and clock insertion encountered in ASIC design process. As a result, designers are able to rapidly progress from their initial RTL to a netlist-level, or placed-gates handoff to eASIC. Designers have the option of performing synthesis using industry standard logic synthesis tools.

FPGA and ASIC designers can try a free 30-day evaluation of eTools 8.1 and Magma logic synthesis software by visiting www.easic.com/etools

About eASIC

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eASIC Corporation

Narinder Lall

(408) 855-9200

narinder@easic.com

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eASIC Announced Immediate Availability of Aeroflex Gaisler’s LEON4 Processor

eASIC — Wed, 03 Mar 2010 07:00:18 +0000

New LEON4 core delivers 50% Performance Increase

Santa Clara, CA – March 03, 2010 – eASIC Corporation, a supplier of NEW ASICs, today announced the immediate availability of Aeroflex Gaisler’s next generation LEON processor, the LEON4, as part of its eZ-IP Alliance Core Library. LEON4 is a high performance, 32-bit processor core based on the SPARC V8 architecture. The new LEON4 core complements the widely used LEON3 processor for high-performance embedded applications across a broad spectrum of demanding consumer and industrial applications.

The power and size optimized LEON4 is fully software compatible with previous LEON processors, yet with a performance increase of up to 50% at the same clock frequency. The LEON4 processor implements single-cycle load/store instructions, as well as static branch prediction. The register file and internal load/store data paths have been extended to 64-bits, while the data cache and bus interface can be either 64- or 128-bit wide. An optional Level-2 (L2) cache has also been added to the architecture, further improving performance on data intensive and multi-core applications. The LEON4 processor delivers up to 1.7 DMIPS per MHz or 0.35 SPECINT2000/MHz.

“We are pleased with the performance of this next generation processor on eASIC silicon,” said Jiri Gaisler, CTO and Founder of Aeroflex Gaisler. “The low cost-point and low up-front development cost of eASIC devices coupled with our LEON4 embedded processing sub-systems now enable an excellent price/performance entry point for custom embedded chip designs.”

“The LEON4 processor core provides our customers with a perfect alternative to traditional soft processor cores from FPGA vendors and prevents customers from being locked into proprietary FPGA vendor IP cores,” said Jasbinder Bhoot, Vice President, Worldwide Marketing at eASIC Corporation. “With Gaisler, customers are provided complete solutions that include CPU cores, peripherals, software tool chain, development boards and technical support.”

Availability

The LEON4 is a high-performance 32-bit SPARC V8 processor that provides computing capabilities to cost-sensitive embedded microcontroller applications. The processor is available as a soft core together with a rich IP library (GRLIB) for instantiations into both FPGAs for prototyping, and eASIC devices for volume production.

Learn more at www.eASIC.com/embedded

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Narinder Lall
(408) 855-9200
narinder@easic.com

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eASIC Slashes Power with low Voltage Device

eASIC — Thu, 21 Jan 2010 17:00:00 +0000

New Devices Reduce Power Consumption up to 40%

Santa Clara, CA – January 21, 2010 - eASIC Corporation, today announced the immediate availability of two new lower power device options for its eASIC Nextreme Family. The NX750LP and NX750 eASIC Nextreme devices are now available with operating voltage down to 1.0V thereby enabling designers to achieve up to 40% lower power consumption. The new 1.0V device options are optimized for applications that require low cost and low power such as smart meters, portable projectors, toys, and handheld medical devices.

eASIC’s Nextreme family is an excellent alternative to standard cell ASIC designs as it provides significantly lower up-front development cost and risk. In addition, eASIC Nextreme provides a lower cost and lower power solution to costly and power hungry FPGAs. The addition of 1.0V device options now enhance the designer’s ability to meet ever shrinking power budgets, achieve longer battery life of their equipment by reducing both static and dynamic power consumption.

“The design wins we are having with these 1.0V devices are giving our customers a market advantage through benefiting from both low cost and low power,” said Jasbinder Bhoot, Vice President of Worldwide Marketing at eASIC Corporation. “We are particularly seeing increased adoption in high volume, hand-held, battery operated applications where we have traditionally not focused,” added Bhoot.

The NX750LP and NX750 low core voltage device options are ideal for designs that require up to 55K Logic Cells (approximately 750K Gates). These devices are available as part of the low cost ASIC-in-a-Box design kits that enable designs to be implemented in as little as 4 weeks.

Pricing and Availability

The 1.0V eASIC Nextreme Devices are available now from eASIC. Pricing starts at $3.95 in high volume. Learn more at www.eASIC.com

About eASIC

Press Contact

eASIC Corporation
Narinder Lall
(408) 855-9200
narinder@easic.com