While FPGAs have been around for nearly 30 years, the overall market still remains a small fraction to that of ASICs suggesting that FPGAs still predominantly remain a vehicle for prototyping or very low volume production. Though standard cell ASICs provide the path to the lowering the device cost for FPGA designs, high up-front NREs, high risk deter many designers from embarking on ASIC designs. Through enabling both low up-front development cost (NRE) and low device cost, eASIC devices provide an alternative path to cost reducing FPGA designs compared to standard cell ASICs.

eASIC Total Cost vs. Low Density FPGA

Low Up-Front Development Cost

eASIC’s ASIC-in-a-Box design kits provide the necessary tools to enable designers to successfully implement eASIC designs. For the cost of a small family car designers receive all the necessary tools, documentation, technical support to complete an eASIC design in addition to 20 assembled and tested prototypes after device tape-out. Engineers provide a verified netlist to eASIC and eASIC takes it from there performing, placement, configuration, routing, RC extraction, static timing analysis, timing closure, ATPG, formal verification, LVS/DRC and tapeout. Customers are expected to review and sign-off at various stages of the flow.

Low Unit Cost

Die size in FPGAs is dominated by SRAM configuration elements which contribute to tha vast majority of the device die size. In eASIC devices, configuration performed using a single Via layer. Vias are considerably more space efficient than SRAM cells and hence do not require any additional die area to be consumed outside the eCell (i.e. the logic element inside eASIC devices.