Total power consumption is generally considered as the sum of two terms: static power and dynamic power. Static power consumption is the power used when the design is idle, and dynamic power is the power consumed by activity in the part. Since neither static nor dynamic power is negligible in most current systems, and they are controlled by different mechanisms, eASIC devices offer significant power reductions compared to similar capacity FPGAs.

Static Power Consumption

Static power consumption, in most CMOS devices is a sum of the leakage currents that exist in the part, as well as a small amount of DC power consumption in analog components such as I/Os and PLLs. In FPGAs, the static power consumption is dominated by the leakage current in the transistors. Leakage current occurs across gates of transistors (through thin oxides) and sub-threshold leakage from drain to source. Both of these leakage mechanisms are worse when the transistor stacks are shallow. Shallow stacks of transistors occur in inverters, buffers, and SRAM cells.

In FPGAs, layout is dominated by SRAM cells that are needed to store the user’s configuration. These SRAM cells are connected to both logic and interconnect elements. For every 6LUT in a Virtex-5 FPGA, there are 64 configuration bits for logic cells and approximately 230 configuration bits for interconnect elements. Similarly, for every 4LUT in a Virtex-4 FPGA, there are 16 configuration bits for logic cells and approximately 180 configuration bits for interconnect elements. This clearly demonstrates how configuration bits within FPGAs are dominated by interconnect elements.

eASIC Nextreme and eASIC Nextreme-2 devices eliminate the SRAM cells associated with configuration of interconnect as the interconnect is determined using only a single Via mask or eBeam configured Vias. In addition, eASIC Nextreme-2 devices also use Vias for configuring LUTs as an additional power saving measure.

eASIC Core Static Power vs. Low Density FPGAs

eASIC Core Static Power vs. High Density FPGAs

Dynamic Power Consumption

The dominant cause of dynamic power consumption is the charging and discharging of capacitance within the part as it manipulates or moves data that is part of the computation. The equation that models this behavior at a particular net is: P = ½CV2αf.

Where C is the capacitance of the user circuit, V is the switching voltage it operates at, alpha is the activity factor of that net (the probability that a this net will switch in a given cycle) and f is the operating frequency of the node. Assuming that we are performing the same computation at the same rate and voltage (voltage is usually determined by available power supplies in the system, and can rarely be optimally scaled), the only way to reduce dynamic power consumption is to reduce either the activity factor or the capacitance.

In general, activity factor is a function of the structure of the implementation. It can be manipulated by design techniques like clock gating and input latching, which can be used in both Virtex-4 and Virtex-5 FPGAs and eASIC Nextreme. The ability to manipulate the activity factor is limited, however, because the activity is what is performing the actual required computation.

What remains is capacitance, and that is where eASIC Nextreme wins big. Capacitance in a digital system exists in interconnect components, interconnect wires, and computational components. eASIC Nextreme dramatically reduces capacitance in all three types of categories:

• Interconnect Components: The mechanism for connecting different wire segments in a FPGA is a multiplexer, composed of a tree of transistors and a final driver. Each of these devices creates additional capacitance that must be switched. The mechanism for connecting wire segments in eASIC Nextreme is a via. Vias have very little capacitance, much less in fact than the wires that are connected by that via. In a eASIC Nextreme device, there is almost no additional capacitance added to the net to provide the regularity and programmability.
• Interconnect Wires: In FPGAs, the interconnect capacitance is generally dominated by the capacitance of active devices in the user’s net, but wire to connect those multiplexers also creates significant capacitance. Because eASIC Nextreme devices are up to 5x smaller than FPGAs of similar density, the reduction in interconnect length, and therefore capacitance, is more than 2X.
• Computational Components: Because total delay in FPGAs is so dominated by interconnect, it is important that every computational component provide as much processing as possible at every stop. This is why the logic component on FPGAs is a large LUT, and includes associated accelerators for common usages (arithmetic, storage, shift register, etc). The inefficiencies of usage of these components is justified by the interconnect delay. As a result, the power consumed by each computational element is burdened by this inefficiency of usage. eASIC Nextreme can achieve greater logic efficiencies due to a lighter weight logic element.

eASIC Core Dynamic Power vs. Low Density FPGAs

eASIC Core Dynamic Power vs. High Density FPGAs

Cyclone, Stratix are trademarks of Altera Corporation.

Spartan, Virtex are trademarks of Xilinx Inc.