DSP Multipliers
eASIC Nextreme-2 provides two options for implementing signal processing functions:
- Logic fabric for high performance parallel implementations
- DSP cores for sequential C-based implementations
High Performance Parallel DSP Implementations
eASIC Nextreme-2 family is ideal for implementing high performance, signal and video/image processing applications. Examples include wireless base stations, professional broadcast, medical imaging and military communications.
Equipped with a 500MHz, logic efficient fabric and bRAMs, eASIC Nextreme-2 does not require designers to use complicated embedded multipliers as with FPGAs. With eASIC Nextreme-2 designers can build optimal architecture implementations that are tailored to the configuration bit-widths that are demanded by the designer’s algorithms.
The table shows raw DSP performance compared to state of the art FPGAs.
| eASIC Nextreme-2 GMACs | Fastest FPGA* GMACs | |
| 10×10 MAC | 1,880 | 1,673 |
| 16×16 MAC | 960 | 941 |
| 18×18 MAC | 624 | 743 |
| 32×32 MAC | 360 | 353 |
* Combination of DSP blocks and logic
DSP cores for C-based implementations
eASIC offers a number of free soft DSP cores from Tensilica that can be used for sequential processing applications.
Tensilica 330HiFi DSP Core
The Diamond 330HiFi core is optimized for digital audio processing. All popular audio codecs have been pre-ported to the Diamond 330HiFi core, which makes it a “drop-in” block for any SOC application requiring high quality, 24-bit audio capability. The Diamond provides high performance processing, while keeping the flexibility and post-silicon programmability of a standard RISC core.
Audio Codec Support includes:
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– Included in core area
– External to core area
Tensilica 545CK DSP Core
The Diamond Standard 545CK is the highest performance licensable DSP IP core. The Diamond 545CK, which combines a base CPU controllers and a DSP containing eight parallel 16-bit single-cycle MAC units, allows system control and industry leading data processing throughput in a single core with a single compiler and single instruction stream. The Diamond 545CK can sustain eight simultaneous MAC operations on independent data pairs per cycle, utilizing the 160-bit vector registers.
– Included in core area
– External to core area
