Low Power Consumption
First generation eASIC Nextreme devices delivered a substantial power consumption advantage versus FPGAs. eASIC Nextreme-2 product family is built using a 45nm low power (LP) process. This process, combined with an enhanced LUT architecture provides substantial static and dynamic power savings for users facing stringent power budgets.
In addition to the quality and reliability benefits associated with lower power solutions, designers using eASIC Nextreme-2 also benefit from being able to use simpler and lower cost components for power and heat removal.
eASIC Nextreme-2 devices deliver up to 80% lower power consumption than state-of-the-art FPGAs. Also, eASIC Nextreme-2 devices provide 50-70% lower power than 90nm eASIC Nextreme, for a given logic density. Many patented enhancements have been made to optimize power in eASIC Nextreme-2 in order to achieve both lower static and dynamic power.
- Akira Itoh, Director of the Fujitsu Circuit Technology Center of Fujitsu Advanced Technologies Ltd
50% Lower Static Power
- GreenPowerVia technology provides the ability to completely power down unused eCells (LUTs) and memory blocks enabling zero leakage.
- Industry’s most power-efficient LUT with no SRAM cells
- Triple-oxide transistors provide perfect blend of speed, low power consumption and density
eASIC Core Static Power vs. High Density FPGAs
50-70% Lower Dynamic Power
- Lower core voltage options – can be 1.1V or 1.2V
- Sleep mode via clock gating
- Dynamic power control through highly granular column-based clock gating.
eASIC Core Dynamic Power vs. High Density FPGAs
