eASIC Nextreme-2 is a family of NEW ASIC devices, manufactured on a 45nm CMOS process, and built using eASIC’s patented single-via customization technology. The eASIC Nextreme-2 family provides ASIC-like performance, power and low unit-cost combined with FPGA-like design flow and rapid delivery of devices.

eASIC Nextreme-2 is built on a breakthrough configurable fabric which combines efficient Look-Up-Table (LUT) based logic with single via-layer customized interconnect. eASIC Nextreme-2 delivers many enhancements and advantages for designers considering standard cell ASICs, FPGAs and ASSPs.

The eASIC Nextreme-2 device family contains two variants optimized to meet different application needs:

  • eASIC Nextreme-2 Family - This family features up to 737K logic elements (eCells), 7.4M equivalent ASIC-gates, and 11.5 Mbits of bRAM
  • eASIC Nextreme-2T Family – This family features up to 580K logic elements (eCells), 5.9M equivalent ASIC-gates, 16.8 Mbits of bRAM, and with up to 32 full duplex high speed SERDES (MGIO) operating up to 6.5Gbps.
eASIC Nextreme-2 Family Advantages
  • Cost Advantage – Significantly lower cost than equivalent density FPGAs
  • Power Consumption Advantage – Up to 80% lower power consumption than FPGAs
  • Memory Advantage – including RAM blocks, register files and ViaROM
  • High Speed I/O Advantage – Up to 32, 6.5 Gbps serial transceivers, 1.25 Gbps LVDS and 1066 Mbps DDR3 I/Os
  • DSP Advantage – Up to 1 TeraMAC/s DSP performance without dedicated DSP multipliers
  • Embedded Processing Advantage – Choose from ColdFire, Tensilica, OpenRISC or LEON processors
  • Superior fabric performance compared to FPGAs
  • Fabric logic not susceptible to single-event configuration-ram failures like in an FPGA.
  • Design Flow Advantage – Approximately 8-10 weeks from RTL to tape-out
  • Manufacturing Advantage – Approximately 8 weeks from tape-out to tested devices
eASIC Nextreme-2 Family Key Features
  • Up to 737K eCells or 1474K LUTs
  • Up to 16.8 Mb of dedicated Block RAM (bRAM)
  • Up to 320Kb of register files
  • Up to 16 PLLs and 32 internal clock domains
  • Up to 52 DLLs
  • Up to 32 6.5Gbps Serial I/Os
  • Up to 792 user configurable I/Os
    • 1.25 Gbps LVDS and 1066 Mbps DDR3 I/Os
    • On-die Termination
    • Dynamic Impedance matching
    • Dynamic Phase Alignment (DPA)
  • Built-in scan chain
  • Fully balanced clock tree
    • JTAG-based boundary and internal scans
    • Core voltage: 1.0V or 1.2V

eASIC Nextreme-2T Components

eASIC Nextreme-2T 45nm Chip Diagram

eASIC Nextreme-2T 45nm Chip Diagram

eASIC Nextreme-2 Components

eASIC Nextreme-2 45nm Chip Diagram

eASIC Nextreme-2 45nm Chip Diagram

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