45nm ASIC Design Made Simple

eASIC Nextreme-2 family delivers low-cost and power associated with traditional ASICs, along with a design flow that is similar to that of an FPGA. When designing eASIC Nextreme-2 devices, designers are not required to perform arduous time and cost intensive tasks such as scan insertion, clock-tree synthesis, IR drop, power-mesh design, signal integrity, design for test, and design for manufacturability. With this simplified design flow, the time from RTL to device tape-out is typically only a few weeks. This enables designers to rapidly cost reduce their FPGA solutions or bring new products to market quickly, then rapidly develop derivative products to cater for changing market requirements.

eTools 9.0 Overview

The eTools 9.0 based design flow enables designers to implement front-end functions of the design flow up-to and including RTL checking and logic synthesis. eTools 9.0 operates in collaboration with logic synthesis software from Synopsys DC. After synthesis, designers use eTools 9.0 to map the I/O pins to their chosen die/package combination, before global placement of the design in order to obtain timing information that is close to the final routed design.

eTools 9.0 Design Flow

The eTools 9.0 based design flow enables designers to simply perform front-end design conversion and back-end implementation. eTools 9.0 operates in collaboration with logic synthesis software from Synopsys DC. After synthesis, designers use the eTools 9.0 ePlanner to map the I/O pins, and floorplan the timing critical portions of their design if required. The placement stage is divided into a global and detailed placement step. Global placement works on a courser granularity of logic fabric detail and with the incremental placement enables fast turns of the design implementation to help designers find the optimal placement and fan out control quickly. The final detailed placer completes the placement stage giving full detail timing estimates and analysis through the parallax timing engine.

The final step of the design process is the design hand-off. Designers have the choice of providing eASIC with a synthesized netlist or a placed gates netlist. In the case of the synthesized netlist design services is required from eASIC in order to close timing on the design.

Hardware and OS Requirements for eTools 9.0

Hardware Requirements

• Memory: 16 GB
• Processor: AMD Opteron or Intel Xeon 64-bit

Operating System

• Centos release 5.3 (final): X86_64, Kernel 2.6.18-128.EL
• Redhat Linux 64-bit: X86_64 RHEL 4.7, kernel 2.6.9-78.EL
• Redhat Linux 64-bit: X86_64 RHEL 4.4, kernel 2.6.9-42.EL
• Redhat Linux 64-bit: X86_64 RHEL 5.5, kernel 2.6.18-194.EL5

Disk Space

• 2 GB for installation of eTools 9.0. Additional space is required for user design files.