Design Entry / Conversion and Synthesis
Design Navigator
The Design Navigator provides FPGA and ASIC designers with an integrated development environment to assist with project management, design conversion and implementation in eASIC Nextreme-2 devices. Users are presented with views into project status, design files, design tasks, errors and warnings. Overall, the user experience and learning curve is very similar to that of FPGA design tools so that minimal training is required in order to transition from expensive and power hungry FPGA solutions.
eZ-IP Wizard
The initial design entry and conversion step is IP replacement and insertion. Designers use eZ-IP Wizard to easily generate memories, FIFOs, I/O and configure the PLLs. Once eASIC-ready RTL has been created, the design is simulated and verified using industry standard tools (Modelsim, NC-Verilog, VCS).
Synthesis
eASIC supports MAGMA Talus and Synopsys Design Compiler.
