Implementation and Verification
eTools provides users with industry standard back end implementation tools to close your designs required timing performance as rapidly as possible, as well as providing users the capability to do detailed analysis of their design. The key tools in the back end design process are:
After synthesis is complete, the actual netlist is used for estimating power consumption using user defined switching activity data. Designers are able to assess static, dynamic, idling power consumption and establish the power savings over their current FPGA design. This tool is a key step in understanding the size of the power saving that can be achieved with eASIC Nextreme-2 45nm devices. This can be as high as 80% over FPGAs on the same process technology.
The ePlanner package view allows designers to select the best IO pins for their design through an interactive GUI. After pin placement SSO details are provided to ensure good signal integrity for the design. This stage can also be assigned automatically to assist users in finding the most optimal pin placement.
The ePlanner (floorplanning) tool allows designers to make preferred and optimal placements of PLLs, pins, memories and performs all required DRC checks.
A major addition in eTools 8.1 was the support for regioning. This enables to optimize the placement of their design through laying out related hierarchical blocks in the design using a simple GUI. Through this guided placement maximum timing performance can be reached in greatly reduced time and without laborious manual optimization.
ePlanner supports numerous types of hierarchical regions including:
- Hard / soft regions
- Exclusive / inclusive / overlapping regions
- Blockages (enables no rectangular regions)
eASIC’s timing driven placement engine ePlacer supports multi-core processors to accelerate run-time by up to 3x for quad core CPUs. Advanced placement algorithms are used in order to achieve the maximum design performance, with limited amount of manual hand placement work. Each release, typically see the performance of ‘push -button’ results increase by 20-30% due to improvements in algorithmic implementation including clock tree synthesis, advanced buffering, OCV and propagated clock analysis automatic worst path optimization.
eTools also provides a placement viewer that is tightly with eTool’s timing analysis engine to assist users in visualizing:
- worst case paths
- design congestion
- fine grain placement editing
Verification
The primary methodology used for design verification is formal verification. For a further level of final design verification simulation libraries for back annotated timing simulation are provided by eTools
See also
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