The eTools 8.1 software suite improvements focus on reducing design conversion and implementation time, simplifying the transition path for designers who adopt the advantages of Nextreme-2 devices. These features include :

• Improved Push-button GUI-based tools to help FPGA designers come rapidly up to speed
• Timing constraints conversion and Auto Memory replacement utilities facilitate faster design conversion from FPGA designs
• Increased IP support in eZ-IP Wizard including:
  • FIFO (synchronous and asynchronous)
  • PLL
  • DDR-2 PHY*
  • LVDS SERDES*
• Interactive Regioning enables hierarchical layout of timing critical portions of design to accelerate timing closure
• Availability of complete placement tool (ePlacer) enabling a placed gates netlist hand-off and greater design control over the design flow
• Multi-Processor core support for 3x faster placement tools
• Improved Quality of Results through improved placement and physical re-synthesis algorithms
• Hierarchical Design Flow allows implementation on large designs to be distributed across numerous team members accelerating to be distributed
• IP Macro Design Flow allows 3^rd party IP vendors or designers to close timing on IP blocks and capture that layout information into the eZ-IP Wizard for distribution of the IP and
• Interactive Placement viewer for timing analysis of design including congestion analysis, fly line / worst case path examination and fine grain placement adjustment
• Physical Re-Synthesis to control net fan-out and fine-grain optimize of the design netlist in order to improve overall timing performance on critical paths

*only available as RTL Verilog. No parametric GUI wizard available.