eASIC nextreme




LEON4 Processor

LEON4 Processor



  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline, with branch prediction
  • 64-bit single-clock load/store operation
  • 64-bit 4-port register file
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data L1 cache (Harvard architecture) with snooping
  • Configurable caches L1: 1 – 4 ways, 1 – 256 kbytes/way. Random, LRR or LRU replacement
  • Configurable L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte – 8 Mbyte
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface, 64- or 128-bit wide
  • Advanced on-chip debug support with instruction and data trace buffer, and performance counter
  • Symmetric Multi-processor support (SMP)
  • Power-down mode and clock gating
  • Robust and fully synchronous single-edge clock design
  • Up to 150 MHz in FPGA and 1500 MHz on 32 nm eASIC device technologies
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • High performance: 1.7 DMIPS/MHz, 2.1 CoreMark/MHz, 0.35 SPECint2000/MHz