eRAM

The eCores contain custom decode logic that together with the eCell LUTs, can be configured into a dual-port memory. Any rectangular arrangement of eCell™ within the eCore™ can be combined to form an eRAM. Dedicated software tools assist the designer in configuring both a single block of memory and multiple blocks of eRAM memories by connecting the eRAM memories together with additional logic. The dedicated decode logic, coupled with priority wire interconnect, creates flexible user defined memories with performance near Standard Cell memories.

bRAM

The bRAM is a dense single port 32Kb memory block whose width is via-configurable into 1, 2, 4, 8, 16, or 32 bits. Multiple bRAM blocks can be connected to form larger memories.

ViaROM™

Each eASIC Nextreme array contains 16KB ROM whose contents are defined by a single via layer. ~2KB are used for eASIC Nextreme self test and configuration, leaving 14KB available for future expansion.

eCore Architecture