eASIC Nextreme is ideal for implementing high performance digital signal processing algorithms like fast fourier transforms (FFT), FIR filters, Numerically Controlled Oscillators (NCO), video scalars, and error correction CODECs. These functions are essential building blocks in signal processing applications including wireless base stations (radio and base band), professional broadcast, video surveillance, medical imaging, and military communications.

Granular High Performance Multipliers using eCells

Equipped with a 250MHz, logic efficient fabric and bRAMs, eASIC’s Nextreme does not require designers to use fixed bit width and complicated embedded multipliers as with FPGAs. With eASIC Nextreme designers are given great freedom to build optimal architecture implementations that are tailored to the configuration bit-widths that required for their algorithms.

This is very different to FPGAs which require users to use a fixed bit width (typically 18 bits) multiplier and often the amount of multipliers is not enough leading to the need for selecting a larger (and more expensive) device. With eASIC Nextreme, simple, portable RTL code empowers the synthesis tools to automatically infer multiplier structures that use only the required number of bits and if one of the multiplier values is constant, an even larger reduction is achieved in eCell usage.

The table shows raw DSP performance compared to state of the art FPGAs.

* = Using the largest Spartan-6 device for comparison (LX150)

High Performance Parallel DSP Algorithms

In digital signal processing, a commonly known advantage of hardware architectures like FPGAs and ASICs over conventional DSPs and processors is the massive boost in performance that is gained through the use of parallelism. eASIC Nextreme devices offer the same capability and with a growing library of eZ-IP users can quickly add FFTs and FIR Filters to their design. Below is are some examples of common DSP algorithms and the performance attained using eASIC Nextreme.