eCell™

The eCell is the main building block of the eASIC Nextreme NEW ASIC architecture, which allows the configuration of logic functions in order to construct complex digital integrated circuits.

eCell features

• Two 3 input Look-Up-Tables (LUTX and LUTY). Each 3 input Look-Up-Tables can be configured to represent any digital function of the three inputs.
• Two NAND gates (NANDX and NANDY). The combination of the NAND gate with a 3 input LUT allows implementation of most 4 input logic functions.
• One 2 input multiplexer (MUX) that can be configured as either a multiplexer or any digital function consisting of 2 inputs. The multiplexer in combination with the 3 input LUTX can represent any function of a 4 input LUT. The multiplexer in combination with the two LUTS allows a wide variety of digital functions.
• One SCAN D Flip Flop (DFF).
• Buffers and Drivers which are used to drive additional logic both within the eCell and in neighboring eCells.

eCore

The eCells are grouped into 8 eUnits, each containing 256 eCells, which altogether form one block called eCore, with total of 2048 (8×256) eCells. Each eUnit or a portion of it can be configured as logic or dual-port memory. Multiple eCores are combined as required to implement a customer’s design.

eCore Architecture