Unlike the traditional programmable routing inside FPGAs, eASIC Nextreme use a patented technique of metal routing with a single via layer. This silicon efficiency and elimination of thousands of SRAM cells directly translates into dramatically lower power consumption for eASIC Nextreme.

Low Static Power Consumption

Static or leakage is the power consumed by the effects of deep sub-micron transistors. This is attributed from source-to-drain or through the gate oxide. This power is consumed even when the transistors are ”off”. The figure below shows the static power consumption of leading FPGAs versus eASIC Nextreme.

eASIC Core Static Power vs. Low Density FPGAs

Low Dynamic Power Consumption

Dynamic power consumption is a direct function of the product capacitance, voltage squared and operating frequency (CV2f). Capacitance is directly impacted by parasitic capacitances of the transistors in the Look-Up-Tables and metal interconnects. As eASIC Nextreme eliminate the need for SRAM-based programmable interconnections, they have considerably fewer interconnect transistors, hence less parasitic capacitances than FPGAs.

eASIC Core Dynamic Power vs. Low Density FPGAs