The eASIC Nextreme family drastically reduces development cost, and turn-around times compared to standard cell ASICs, while significantly reducing power consumption and unit cost for designs that start off as FPGAs.

eASIC Nextreme devices use a patented breakthrough concept combining configurable Look-up Table (LUT) cells with customized single-via interconnect. The interconnect is customized quickly and inexpensively with an alternative lithography approach called Direct-Write eBeam.

Direct-Write eBeam flexibility enables different patterns to be easily printed directly onto the same wafer. The resulting rapid turnaround time, make eASIC Nextreme NEW ASICs an ideal solution for both for prototyping, low-volume production. When a customer design goes to high volume, a single via mask can be created for customization.

eASIC Nextreme Advantages

• Low up-front charges
• Up to 80% lower power than FPGAs
• Significantly lower device cost than FPGAs
• FPGA-like design flow
• Inexpensive design software
• Fast turnaround for devices

eASIC Nextreme Key Features

• 300 MHz system performance
• Up to 5M Combination of Logic & Memory Gates
• Up to 358K eCells or 700K LUTs
• Up to 5.6 Mb of dedicated Block RAM (bRAM)
• Up to 5.6 Mb of distributed dual-port memory (eRAM)
• Up to 10 PLLs and 32 internal clock domains
• Up to 20 DLLs
• Up to 790 user configurable I/Os
  • 533 Mbps DDR2 & 400 Mbps DDR1
  • 800 Mbps LVDS
  • On-die Termination
  • Dynamic Impedance matching
• Built-in scan chain
• Core voltage: 1.2V or 1.3V

eASIC Nextreme Components

eASIC Nextreme devices contain a variety of features and components for maximizing customer benefits.

eASIC Nextreme 90nm Chip Diagram

PLLs

Each eASIC Nextreme array has a number of custom single via configurable Phase Lock Loop (PLL) blocks as part of the built-in clock structure. The user can generate a variety of phase and frequency related clocks from primary input clocks, and distribute them throughout the NEW ASIC logic fabric using the built-in low skew clock distribution system.

DLLs

Each eASIC Nextreme device contains a number of Delay Locked Loops (DLLs) that generate precise degrees of clock phase shifting and can be used for high speed interfaces such as DDR, DDR2 and QDR. The DLL also contains programmable gate delays which can be used to compensate for external data path or clock tree delays.

Test Automation

Test is always a cumbersome afterthought in traditional ASICs but it is not necessary with FPGAs. ASIC users not only have to generate patterns for testing their parts during manufacturing, but are also required to extend such efforts to incoming part testing and final product bring-up diagnostics. The eASIC Nextreme unique architecture provides automated testing and does not require the user to generate custom test vectors.

Every eASIC Nextreme device has a built-in scan chain through all flip-flops. The scan-in and scan-out lines allow for easily running ATPG vectors. The bRAM blocks are fully tested by internal memory self-test routines.

eASIC Nextreme Routing Capability

The eASIC Nextreme logic customization is achieved using a single via layer to connect the vertical and horizontal routing segments. The components within each eCell have both predefined interconnect and user defined interconnect for routing. This combination provides a powerful approach to implementing complex digital functions efficiently using a single customized via layer.

eASIC’s NEW ASIC fabric features regular arrays of coarse-grained programmable cells, uniquely customized with a single via layer. This routing customization technique employs four metal layers, utilizing hierarchical structure where two layers (Metal 6 and Metal 7) comprises short segments and two layers (Metal 4 and Metal 5) comprise long segments, which only periodically access the short ones to allow connection thereof. This innovative customization technique, as implemented on eASIC’s NEW ASIC fabric, results in high density routing.