The starting point for most easicopy designs is a eASIC Nextreme or Nextreme-2 design. This enables eASIC engineers to leverage much of the work that has already been done from a design that is already successfully in production. In addition, this helps to reduce the overall time to production for the easicopy design.

The easicopy design flow is shown below. At the front end it requires a eASIC Nextreme or Nextreme-2 synthesized netlist and an SDC timing constraints file. After initial synthesis, the design is taken through a traditional cell-based ASIC flow by eASIC engineers. This includes Design For Test (DFT) insertion and synthesis, and then back-end physical implemention which includes floorplanning, I/O ring design, power mesh design, timing driven place and route, timing closure, parasitic extraction, final STA, and tapeout readiness.

Migration to easicopy™ Flow

eASIC engineers have extensive experience in converting FPGA designs to via-programmable eASIC Nextreme or Nextreme-2 NEW ASIC, and then eASIC Nextreme or Nextreme-2 NEW ASIC designs to cell-based, easicopy ASIC.