- Zero wait states burst mode
- Full bus Master/Target functionality
- Single interrupt support
- Implements 64 bytes of PCI Configuration Space registers;
Can be extended to 256 bytes
- Target portion supports up to six base Address Registers with both I/O
and Memory space decoding from 16 bytes up to 2 GB
- Support of backend initiated target retry, disconnect and abort
- Parity generation and parity error detection.
- Both Target and Master supported commands are: Configuration Read, Configuration
Write, Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read
Line (MRL) & I/O Read, I/O Write.
- 64-bit DMA Controller Core.