Principal DFT Engineer
Title: Principal DFT Engineer
Location: Santa Clara, CA, USA
Job ID: 030117
Reports to: Director, Engineering
The Principal DFT Engineer will be responsible for DFT methodology in the Company test pattern generation including JTAG, boundary scan, memory BIST, scan patterns.
Essential Functions and Competencies
This position is responsible for using STA to identify critical test paths and logic areas. After running vector generation, simulation and qualification you will help bring up the test program on the ATE working closely with Test Engineering team. Yield data analysis will also play a large part in this job to improve our bottom line. Hands on participation in the vector generation process is required.
- Work with architecture team, IP team and Circuit team to understand design implementation and define DFT integration strategy for next generation silicon product
- Lead the definition and development of DFT flow to centralize the pattern generation methodology and verification for both DC & AC scans in bypass & edt mode, BIST and etc.
- Debug, analyze and provide innovative solutions to improve ATPG coverage in both Stuck-At and Transition Faults
- Develop STA flow for shift & capture testmode and boundary scan mode
- Define DPPM calculation methodology and determine targeted ATPG coverage for each design
- Work with Test Engineering team to resolve ATPG pattern failures on ATE
- Work with Test Engineering team to root-cause and provide ATPG patterns or advise targeted test to cover customer RMA.
- Strong technical skills
- Analytical thinker
- Leadership / mentoring
- Achievement against goals
Manager / Supervisory Responsibilities
This position has no direct supervisory responsibilities, but does serve as a coach and mentor for other positions in the department.
No or minimal travel is expected for this position.
Required Education and Experience
- Degree in Computer Science or Electrical/Electronic Engineering with minimum 12 years of working experience in VLSI DFT
- Experience in Verilog/VHDL including behavior model construction and verification is essential
- Experience in industrial ATPG tools, logic simulation tools
- Experience in Perl, TCL, C/C++ and Linux/Unix software development will be added advantage
- Deep understanding of SCAN-based test methodologies including speed defect delay testing, bridge fault testing, etc.
- Deep understanding of JTAG test methods including 1149.1 & 1149.6
- Working understanding of MEMORY BIST test methods for embedded memories
- Deep understanding of test methods for embedded IP cores
- Expert working knowledge of standard test tools and flows
- Ability to automate the design flow via shell scripts, perl scripts, etc.
- Completion of at least 10 projects through ramp to production
- Expertise with Mentor’s DFT flow preferred.
Additional Eligibility Qualifications
- Must be well organized and a self-starter, and have strong work ethics
- Detail oriented, professional attitude, reliable
- Ability to interact with all levels in a professional manner
- Ability to work independently, also with local and international teams, in a fast-paced and high volume environment, with emphasis on accuracy and timeliness
- Strong communication skills (written and verbal).
eASIC provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, national origin, age, disability or genetics. In addition to federal law requirements, eASIC complies with applicable state and local laws governing nondiscrimination in employment in every location in which the company has facilities.
Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities and activities may change at any time with or without notice.
Click here to submit your resume.