Principal IP & Systems Engineer
Position: Principal IP & Systems Engineer
Location: Santa Clara, CA, USA
Job Posting: 02062017
This Principal IP & Systems Engineering position, reports directly into the Sr. Director, IP & Systems Engineering, will be responsible for the design and simulation for a variety of core IP’s. They will interface with IP vendors, customers and various teams inside eASIC to ensure a successful and competitive product. All work is expected to be of highest production quality and is expected to enable implementation teams to deliver in a timely fashion to hit market windows. The position requires a self-driven candidate with very good knowledge on design and verification as well as good communication skills.
- Perform integration of Ethernet MAC/PCS cores with eASIC PMA according to the customer requirements
- Develop, maintain and improve the verification environment for the integrated IPs
- Perform implementation including SDC development, review timing with the IP vendor and provide timing constraints integration support to the customer
- Develop and maintain a checklist for the IPs which should be reviewed as part of the signoff process with the IP vendor and the customer
- Define and develop the AN/LT solution for IPs integrated with the eASIC PMA; develop a scalable solution to be fit various IPs with minor modifications
- Able to develop simple C firmware code for AN/LT control solutions using embedded CPUs
- Collaborate with various teams across the company as well as interact with customers.
- Detail Oriented
- Strong Written and Verbal Communication skills
- Strong Collaboration skills
- Strong Technical Skills (knowledge of Verilog, SystemVerilog or VHDL)
Manager / Supervisory Responsibilities
This position has no direct supervisory responsibilities, but does serve as a coach and mentor for other positions in the department.
Minimal travel is expected for this position.
Required Education and Experience
- BSEE required; MSEE preferred
- Minimum of 8 years of professional experience in a semiconductor industry, in a research and development environment
- Strong Linux scripting (Python/Perl) & UVM experience
- Deep understanding of DDR3/DDR4 protocols and previous experience in validating subsystems including both the PHY and Controller
- Strong experience designing or verifying IPs like: Ethernet MACs, PCIe or SATA Controllers
- Proven track record of multiple successful tape-outs
- Experienced with both front-end and back-end chip design
- Passion for technology, commitment to driving results and ability to get into the details while
- Self-starter with the ability to manage multiple projects with simultaneous time sensitive deadlines
- Ability to function independently while maintaining strong team-work and collaborative approach
- Highly motivated with strong interpersonal skills
- Strong written and verbal communication skills.
eASIC provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, national origin, age, disability or genetics. In addition to federal law requirements, eASIC complies with applicable state and local laws governing nondiscrimination in employment in every location in which the company has facilities.
Please note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities and activities may change at any time with or without notice.
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