eASIC nextreme




SPI Master

SPI Master



  • Full duplex synchronous serial data transfer
  • Variable length of transfer word up to 128 bits
  • MSB or LSB first data transfer
  • Technology independent Verilog
  • Fully synthesizable
  • Rx and Tx on both rising or falling edge of serial clock independently
  • 8 slave select lines
  • Fully static synchronous design with one clock domain
  • Technology independent Verilog